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Details, datasheet, quote on part number:240VA
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Datasheet text preview:
ispGDX 240VA
TM
In-System Programmable 3.3V Generic Digital Crosspoint
TM
Features
· IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY -- Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement -- "Any Input to Any Output" Routing -- Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation -- Space-Saving PQFP and BGA Packaging -- Dedicated IEEE 1149.1-Compliant Boundary Scan Test · HIGH PERFORMANCE E2CMOS® TECHNOLOGY -- 3.3V Core Power Supply -- 4.5ns Input-to-Output/4.5ns Clock-to-Output Delay -- 200MHz Maximum Clock Frequency -- TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable) -- Low-Power: 16.5mA Quiescent Icc -- 24mA IOL Drive with Programmable Slew Rate Control Option -- PCI Compatible Drive Capability -- Schmitt Trigger Inputs for Noise Immunity -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology · ispGDXVATM OFFERS THE FOLLOWING ADVANTAGES
Functional Block Diagram
I/O Pins D
ISP Control
I/O Pins C
I/O Pins A
I/O Cells
Global Routing Pool (GRP)
I/O Cells
· FLEXIBLE ARCHITECTURE -- Combinatorial/Latched/Registered Inputs or Outputs -- Individual I/O Tri-state Control with Polarity Control -- Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (60) -- Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns) -- Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX -- Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins -- Outputs Tri-state During Power-up ("Live Insertion" Friendly)
VA
-- 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) -- Change Interconnects in Seconds
D
A
· DESIGN SUPPORT THROUGH LATTICE'S ispGDX DEVELOPMENT SOFTWARE -- MS Windows or NT / PC-Based or Sun O/S -- Easy Text-Based Design Entry -- Automatic Signal Routing -- Program up to 100 ISP Devices Concurrently -- Simulator Netlist Generation for Easy Board-Level Simulation
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
N
1
C
Boundary Scan Control
Description
The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including: · Multi-Port Multiprocessor Interfaces · Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX) · Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) · Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 4.5ns and clock-to-output delays of 4.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs
ED
I/O Pins B
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
gdx240va_02
Specifications ispGDX240VA
Description (Continued)
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. Table 1. ispGDXV/VA Family Members In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later. Programm a b l e output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise. All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands. The ispGDXVA I/Os are designed to withstand "live insertion" system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for "live insertion," absolute maximum rating conditions for the Vcc and I/O pins must still be met.
D
VA
80 20 20 20 20 2 1 1 4 1
ispGDX80VA
N
2
C
160 40 40 40 40 4 1 1 4 1
ispGDXV/VA Device ispGDX160V/VA ispGDX240VA 240 60 60 60 60 4 1 1 4 1
A
I/O-OE Inputs* EPEN TOE RESET
I/O Pins
I/O-CLK / CLKEN Inputs* I/O-MUXsel1 Inputs* I/O-MUXsel2 Inputs* Dedicated Clock Pins**
BSCAN Interface Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA 208-Ball fpBGA 272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to 25% of the I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices.
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Specifications ispGDX240VA
Architecture
The ispGDXVA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol. The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in a 240-I/O ispGDXVA, each data input can connect to one of 60 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 60 out of 240). MUX0 and MUX1 can be driven from either MUXsel1 or MUXsel2.
Logic "0" Logic "1"
240 I/O Inputs
N VA
E2CMOS Programmable Interconnect
I/OCell 0
I/O Cell 1
C
I/O Cell 239 I/O Cell 238
· · ·
To 2 Adjacent I/O Cells above
Figure 1. ispGDXVA I/O Cell and GRP Detail (240 I/O Device)
ED
Bypass Option
Register or Latch
D
From MUX Outputs of 2 Adjacent I/O Cells N+2 N+1 4x4 Crossbar Switch
4-to-1 MUX
M0 M1 M2 M3 MUX0 MUX1 To 2 Adjacent I/O Cells below
Prog. Prog. Pull-up Bus Hold Latch (VCCIO)
A
I/O Group A I/O Group B I/O Group C I/O Group D
A B D CLK
CLK_EN Reset
C R
Prog. Open Drain 2.5V/3.3V Output Prog. Slew Rate
I/O Pin
Q
N-1 N-2
· · · · · ·
From MUX Outputs of 2 Adjacent I/O Cells
Boundary Scan Cell
I/O Cell N
· · ·
I/O Cell 118
······
I/O Cell 121
I/O Cell 119
120 I/O Cells 240 Input GRP
Inputs Vertical Outputs Horizontal Global Y0-Y3 Reset Global Clocks / Clock_Enables
I/O Cell 120
120 I/O Cells
ispGDXVA architecture enhancements over ispGDX (5V)
3
Specifications ispGDX240VA
I/O MUX Operation
MUX1 0 0 1 1 MUX0 0 1 1 0 Data Input Selected M0 M1 M2 M3
allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The relationship between the [N+i] adjacent cells and A, B, C and D inputs will vary depending on where the I/O cell is located on the physical die. The I/O cells can be grouped into "normal" and "reflected" I/O cells or I/O "hemispheres." These are defined as:
Device ispGDX80VA ispGDX160V/VA ispGDX240VA Normal I/O Cells B9-B0, A19-A0, D19-D10 B19-B0, A39-A0, D39-D20 B29-B0, A59-A0, D59-D30 Reflected I/O Cells B10-B19, C0-C19, D0-D9 B20-B39, C0-C39, D0-D19 B30-B59, C0-C59, D0-D29
I/O cell index increases in this direction
MUX Expander Using Adjacent I/O Cells
The ispGDXVA allows adjacent I/O cell MUXes to be cascaded to form wider input MUXes (up to 16 x 1) without incurring an additional full Tpd penalty. However, there are certain dependencies on the locality of the adjacent MUXes when used along with direct MUX inputs.
B0
B29
B30
B59
I/O cell 119 I/O cell 120
Adjacent I/O Cells
E x p a n s i o n inputs MUXOUT[n-2], MUXOUT[n-1], MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard A, B, C and D MUX inputs, and
Direct and Expander Input Routing
Table 2 also illustrates the routing of MUX direct inputs that are accessible when using adjacent I/O cells as inputs. Take I/O cell D33 as an example, which is also shown in Figure 3.
4
C0
I/O cell index increases in this direction
A
The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the "A" path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the "B" path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input pins (Yx). The programmable polarity Clock Enable input to the register can be programmed to connect to any of the I/O-CLK/CLKEN input pin set or to the global clock enable inputs (CLKENx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low.
VA
N
Table 2 shows the relationship between adjacent I/O cells as well as their relationship to direct MUX inputs. Note that the MUX expansion is circular and that I/O cell B30, for example, draws on I/Os B29 and B28, as well as B31 and B32, even though they are in different hemispheres of the physical die. Table 2 shows some typical cases and all boundary cases. All other cells can be extrapolated from the pattern shown in the table. Figure 2. I/O Hemisphere Configuration of ispGDX240VA
I/O cell 0 I/O cell 239
C
A0 A59
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D59 D30
Flexible mapping of MUXselx to MUXx allows the user to change the MUX select assignment after the ispGDXVA device has been soldered to the board. Figure 1 shows that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX implementations.
D29
D0
D
C59
Specifications ispGDX240VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX240VA, I/O D33
ispGDX240VA I/O Cell I/O Group A D31 MUX Out I/O Group B D32 MUX Out I/O Group C D34 MUX Out I/O Group D D35 MUX Out 4x4 Crossbar Switch S1 S0
.m0 .m1 .m2 .m3
Special Features Slew Rate Control
All output buffers contain a programmable slew rate control that provides software-selectable slew rate options.
Open Drain Control
D33
It can be seen from Figure 3 that if the D11 adjacent I/O cell is used, the I/O group "A" input is no longer available as a direct MUX input. The ispGDXVA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized. Table 2. Adjacent I/O Cells (Mapping of ispGDX240VA)
Pull-up Resistor
All pins have a programmable active pull-up. A typical resistor value for the pull-up ranges from 50k to 80k.
VA
B29 B30 B31 B32 D25 D26 D27 D28 D31 D32 D33 D34 B27 B28 B29 B30 B28 B29 B30 B31 D24 D25 D26 D27 D32 D33 D34 D35 B28 B29 B30 B31
Data A/ Data B/ Data C/ Data D/ MUXOUT MUXOUT MUXOUT MUXOUT B30 B31 B32 Reflected I/O Cells B33 D26 D27 D28 D29 D30 D31 D32 Normal I/O Cells D33 B26 B27 B28 B29 B32 B33 B34 B35 D28 D29 D30 D31 D28 D29 D30 D31 B24 B25 B26 B27
D
B31 B32 B33 B34 D27 D28 D29 D30 D29 D30 D31 D32 B25 B26 B27 B28
A
N
5
C
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds the previously driven state when all drivers connected to the pin (including the pin's output driver as well as any other devices connected to the pin by external bus) are tristated.
User-Programmable I/Os
T h e ispGDX240VA features user-programmable I/Os supporting either 3.3V or 2.5V output voltage level options. The ispGDX240VA uses a VCCIO pin to provide the 2.5V reference voltage when used.
PCI Compatible Drive Capability
The ispGDX240VA supports PCI compatible drive capability for all I/Os.
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All output buffers provide a programmable Open-Drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip Open-Drain or Open-Collector buffer. Wire-OR logic functions can be performed at the printed circuit board level.
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