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Part: ISPLSI883
Category:
Description:
Company: Lattice Semiconductor Corp.
Datasheet: Download ISPLSI883 datasheet File size : 1264 kB
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ispLSI 1048C/883
®
In-System Programmable High Density PLD Features
· HIGH-DENSITY PROGRAMMABLE LOGIC -- 8000 PLD Gates -- 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables -- 288 Registers -- High-Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Security Cell Prevents Unauthorized Copying · HIGH PERFORMANCE E2CMOS® TECHNOLOGY -- fmax = 50 MHz Maximum Operating Frequency -- tpd = 22 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology -- 100% Tested at Time of Manufacture · IN-SYSTEM PROGRAMMABLE -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging · COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity · ispDesignEXPERTTM LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0 Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5
Output Routing Pool
A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
Logic
DQ
Global Routing Pool (GRP)
Array
DQ
GLB
D4 D3 D2 D1 D0
DQ
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
CLK
0139G1A-isp
Description
The ispLSI 1048C/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD883. This military grade device contains 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048C/883 features 5-Volt ins y s t e m programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, and the interconnect to provide truly reconfigurable systems. Compared to the ispLSI 1048, the ispLSI 1048C/883 offers two additional dedicated inputs and two new Global Output Enable pins. The basic unit of logic on the ispLSI 1048C/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in figure 1. There are a total of 48 GLBs in the ispLSI 1048C/883 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1048CMIL_01
1
Output Routing Pool
A1
DQ
D6
Specifications ispLSI 1048C/883
Functional Block Diagram
Figure 1. ispLSI 1048C/883 Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
GOE0 GOE1
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 9
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0
IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60
D7
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
Output Routing Pool (ORP)
D6
Output Routing Pool (ORP)
D5
I/O 59 I/O 58 I/O 57
D4 D3 D2 D1 D0
lnput Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
C0
C1
C2
C3
C4
C5
C6
C7
Clock Distribution Network
Output Routing Pool (ORP) Megablock Input Bus
ispEN
IN2 SDO/ IN3
Output Routing Pool (ORP) Input Bus
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
I/O I/O I/O I/O 16 17 18 19
I/O I/O I/O I/O 20 21 22 23
I/O I/O I/O I/O 24 25 26 27
I/O I/O I/O I/O 28 29 30 31
IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35
I/O I/O I/O I/O 36 37 38 39
I/O I/O I/O I/O 40 41 42 43
I/O I/O I/O I/O 44 45 46 47
YYYY 0123
0139F(2)-48B-isp
The device also has a 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs have selectable polarity, active high or active low. The signal voltage levels are TTL-compatible, and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock as shown in figure 1. The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048C/883 device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048C/883 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048C/883 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals.
2
Specifications ispLSI 1048C/883
Absolute Maximum Ratings 1
Supply Voltage Vcc .. -0.5 to +7.0V Input Voltage Applied ...... -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ........ -65 to 150°C Case Temp. with Power Applied ..... -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Military/883 TC = -55°C to +125°C MIN. 4.5 0 2.0 MAX. 5.5 0.8 Vcc + 1 V V
0005A mil.eps
UNITS
VC C VI L VI H
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O and Clock Capacitance MAXIMUM1 10 10 UNITS pf pf TEST CONDITIONS VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006mil
C1 C2
1. Characterized but not 100% tested.
Data Retention Specifications
PARAMETER Data Retention Erase/Reprogram Cycles MINIMUM 20 10000 MAXIMUM -- -- UNITS Years Cycles
Table 2- 0008B
3
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