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Part: LC51024MC-75F484I
Category:
FPGAs/PLDs
-> PLDs (Programmable Logic Devices)
-> CPLDs (Computer PLD)
Description: Ispxpld 5512MV (3.3V)512 Macrocells
Company: Lattice Semiconductor Corp.
Datasheet: Download LC51024MC-75F484I datasheet File size : 81 kB
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Datasheet text preview:
w
5 ispXPLD
TM
000MX Family
Data Sheet
3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLDTM Family
July 2003
Features
Flexible Multi-Function Block (MFB) Architecture
· · · · · SuperWIDETM logic (up to 136 inputs) Arithmetic capability Single- or Dual-port SRAM FIFO Ternary CAM
Expanded In-System Programmability (ispXPTM)
· Instant-on capability · Single chip convenience · In-System Programmable via IEEE 1532 Interface · Infinitely reconfigurable via IEEE 1532 or sysCONFIGTM microprocessor interface · Design security
sysCLOCKTM PLL Timing Control
· Multiply and divide between 1 and 32 · Clock shifting capability · External feedback capability
High Speed Operation
· 4.0ns pin-to-pin delays, 300MHz fMAX · Deterministic timing
Low Power Consumption
· Static power: 20 to 50mA (1.8V) 30 to 60mA (2.5/3.3V) · 1.8V core for low dynamic power
sysIOTM Interfaces
· LVCMOS 1.8, 2.5, 3.3V Programmable impedance Hot-socketing Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none) Open drain operation · SSTL 2, 3 (I & II) · HSTL (I, III, IV) · PCI 3.3 · GTL+ · LVDS · LVPECL · LVTTL Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX Macrocells Multi-Function Blocks Maximum RAM Bits Maximum CAM Bits sysCLOCK PLLs tPD (Propagation Delay) tS (Register Set-up Time) tCO (Register Clock to Out Time) fMAX (Maximum Operating Frequency) System Gates I/O s Packages 256 fpBGA 256 8 128K 48K 2 4.0ns 2.2ns 2.8ns 300MHz 75K 141
Easy System Integration
· 3.3V (5000MV), 2.5V (5000MB) and 1.8V (5000MC) power supply operation · 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces · IEEE 1149.1 interface for boundary scan testing · sysIO quick configuration · Density migration · Multiple density and package options · PQFP and fine pitch BGA packaging
ispXPLD 5512MX 512 16 256K 96K 2 4.5ns 2.9ns 3.0ns 250MHz 150K 149/193/253 208 PQFP 256 fpBGA 484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX 768 24 384K 144K 2 5.0ns 3.0ns 3.8ns 240MHz 225K 193/317 256 fpBGA 484 fpBGA 1,024 32 512K 192K 2 5.2ns 3.0ns 3.8ns 235MHz 300K 317/381
484 fpBGA 672 fpBGA
Note: ispXPLD 5256MX/5512MX/51024MX information is preliminary. ispXPLD 5768MX information is advance.
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
5kmx_06
Lattice Semiconductor
Figure 1. ispXPLD 5000MX Block Diagram
PROGRAM
ispXPLD 5000MX Family Data Sheet
TDO VCCJ
GND
TMS
TCK
VCC
ISP Port VCCO0 VREF0 sysIO Bank 0
OSA
TDI
VCCO3 VREF3 MFB MFB sysIO Bank 3
OSA
MFB GCLCK0 VC C P GNDP GCLK1 sysIO Bank 1
Optional sysCONFIG Interface
MFB GCLCK3 Global Routing Pool (GRP)
sysCLOCK PLL 0
sysCLOCK PLL 1 GCLK2
MFB
MFB
sysIO Bank 2
RESET GOE0 GOE1
VREF2 VCCO2
OSA
OSA
VREF1 VCCO1
MFB
MFB
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic Devices (XPLDs). These devices extend the capability of Lattice's popular SuperWIDE ispMACH 5000 architecture by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers. The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading performance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and operating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing. The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps users meet the challenge of today's mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases integration into today's complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool. Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD 2
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs are provided to allow the synthesis of new clocks and control of clock skews.
Multi-Function Block (MFB)
Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are: · · · · · · SuperWIDE Logic Mode True Dual-port SRAM Mode Pseudo Dual-port SRAM Mode Single-por t SRAM Mode FIFO Mode Ternary CAM Mode
The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multifunction array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs data along with certain control functions to the macrocells. Output signals can be routed internally for use elsewhere in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various configurations are described in more detail in the following sections. Figure 2. MFB Block Diagram
Cascade In
CLK0 CLK1 CLK2 CLK3 Reset
To Routing
Multifunction Array True Dual Port RAM
(8,192 bit)
Single Port RAM
(16,384 bit)
FIFO
(16,384 bit)
Ternary CAM
(128*48)
Logic
(68 Input * 164 Product Term Array, 32 MC)
PTOE Sharing Cascade Out
3
To I/O via OSA
(16,384 bit)
32 Feedback Signals
Pseudo Dual Port RAM
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