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Details, datasheet, quote on part number:LC51024VG-5F676C
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Datasheet text preview:
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ispMACH
December 2001
TM
000VG Family
3.3V In-System Programmable uperWIDE igh Density PLDs
TM
SuperBIG,
TM
Data Sheet
Features
High Density
· 768 to 1,024 macrocells · 196 to 384 I/Os
Ease of Design
· Product term sharing · Extensive clocking and OE capability
Easy System Integration
· · · · · · · · 3.3V power supply Hot socketing Input pull-up, pull-down or bus-keeper Open drain capability Slew rate control Macrocell-based power management IEEE 1149.1 boundary scan testable In-system programmable via IEEE 1532 ISC compliant interface
sysCLOCKTM PLL Timing Control
· · · · Multiply and divide factors between 1 and 32 Clock shifting capability ± 3.5ns in 500ps steps Multiple output frequencies External feedback capability for board-level clock deskew · LVDS/LVPECL clock input capability
High Speed Logic Implementation
· SuperWIDE 68-input logic block · Up to 160 product terms per output · Hierarchical routing structure provides fast interconnect
ispMACH 5000VG Introduction
The ispMACH 5000VG represents the third generation of Lattice's SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance for typical designs over architectures with fewer inputs. The ispMACH 5000VG takes the unique benefits of the SuperWIDE architecture and extends it to higher densities referred to as SuperBIG, by using the combination of an innovative product term architecture and a twotiered hierarchical routing architecture. Additionally, sysCLOCK and sysIO capabilities have been added to maximize system-level performance and integration.
sysIOTM Capability
· · · · · · · · · · · LVCMOS 1.8, 2.5 and 3.3 LVTTL SSTL 2 (I & II) SSTL 3 (I & II) CTT 3.3, CTT 2.5 HSTL (I & III) PCI-X, PCI 3.3 GTL+ AGP-1X 5V tolerance Programmable drive strength
Table 1. ispMACH 5000VG Family Selection Guide
ispMACH 5768VG Macrocells User I/O Options tPD (ns) tS Set-up with 0 Hold (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Package 768 196/304 5.0 3.0 4.4 178 3.3V 256-ball fpBGA 484-ball fpBGA ispMACH 51024VG 1,024 304/384 5.0 3.0 4.4 178 3.3V 484-ball fpBGA 676-ball fpBGA
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Lattice Semiconductor
Figure 1. Functional Block Diagram
RESETB GOE1 GOE2 TOE
ispMACH 5000VG Family Data Sheet
I/O Bank 0
I/O Bank 3
GLB SRP
VCCO0 VREF0 GCLK0
GLB GLB
GLB SRP GLB
GLB GLB
VCCO3 VREF3 GCLK3
GLB
GLB SRP GLB
GLB GLB
GLB SRP GLB
GLB GLB
VCCP0 GNDP0
PLL0
Global Routing Pool
PLL1
VCCP1 GNDP1
GLB SRP
GCLK1 VREF1 VCCO1
GLB GLB
GLB SRP GLB
GLB GLB
GCLK2 VREF2 VCCO2
GLB
GLB SRP GLB
I/O Bank 1
GLB GLB
GLB SRP GLB
I/O Bank 2 TDI TDO TMS TCK VCCJ
GLB GLB
Overview
The ispMACH 5000VG devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH 5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP). Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow designers to create large designs in a single device without compromising performance. Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups of five product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Sharing Array. The macrocell is designed to provide flexible clocking and control functionality with the capability to select between global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell. All I/Os in the ispMACH 5000VG family are sysIOs, which are split into four banks. Each bank has a separate I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging interface standards. Within a bank, inputs can be set to a variety of standards, providing the reference voltage requirements of the chosen standards are compatible. Within a bank, the outputs can be set to differing standards, providing the I/O power supply voltage and the reference voltage requirements of the chosen standard are compatible. Support for this wide range of standards allows designers to achieve significantly higher board-level performance compared to the more traditional LVCMOS standards.
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Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
The ispMACH5000VG devices also contain sysCLOCK Phase Locked Loops (PLLs) that provide designers with increased clocking flexibility. The PLLs can be used to synthesize new clocks for use on-chip or elsewhere within the system. They can also be used to deskew clocks, again both at the chip and system levels. A variable delay line capability further improves this and allows designers to retard or advance the clock in order to tune set-up and clock-to-out times for optimal results. The ispMACH 5000VG Family Selection Guide (Table 1) details the key attributes and packages for the ispMACH 5000VG devices.
ispMACH 5000VG Architecture
The ispMACH 5000VG Family of In-System Programmable High Density Logic Devices is based on segments containing four Generic Logic Blocks (GLBs) and a hierarchical routing pool (GRP) structure interconnecting the segments. A segment routing pool (SRP) connects each GLB in a segment allowing the maximum flexibility and speed. Outputs from the GLBs drive the Segment Routing Pool (SRP) and the Global Routing Pool (GRP). Enhanced switching resources are provided to allow signals in the Segment Routing Pool to drive any or all the GLBs in the segment. Optimal switching is provided to allow all signals in the Global Routing Pool to be routed to any or all SRPs. This mechanism allows fast, efficient connections across the entire device.
Segment
Each segment contains four GLBs and a segment routing pool (SRP). Each GLB has 32 internal feedback outputs and 16 external feedback outputs, for a total of 48 outputs from each GLB feeding the SRP. The SRP contains up to 384 signals, 48 from each GLB and 192 from the GRP, with full routing capability. This routing scheme maximizes the flexibility and speed of the device without sacrificing the routing. Figure 2. Segment
To GRP To GRP
48
Clocks 4
48 48 48
Clocks
GLB
68
Clocks 4
48
GLB
68 48
To GRP
Segment Routing Pool (SRP)
68
GLB
4
48
GLB
68 48
To GRP
Clocks 4
192 From GRP
Generic Logic Block
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three control product terms. The GLB has 68 inputs from the Segment Routing Pool, which are available in both true and complement form for every product term. The three control product terms are used for shared reset, clock and output enable functions. Figure 3 shows the structure of the GLB from the macrocell perspective. This is referred to as a macrocell slice. There are 32 macrocell slices per GLB.
AND-Array
The programmable AND-Array consists of 68 inputs and 163 output product terms. The 68 inputs from the SRP are used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be connected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the DualOR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset and Shared PT OE. Every set of five product terms from the 160 logic product terms forms a product term cluster start3
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