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Details, datasheet, quote on part number:LC5128B-10T128I
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ispMACH 000B Family
2.5V In-System Programmable SuperWIDETM igh Density PLDs
September 2002 Data Sheet
Features
High Speed Logic Implementation
· SuperWIDE 68-input logic block · Up to 35 product terms per output · Single-level Global Routing Pool (GRP) LVCMOS 1.8, 2.5 and 3.3 LVTTL SSTL 2 (I and II) SSTL 3 (I and II) CTT 3.3, CTT 2.5 HSTL (I and III) PCI 3.3 GTL+ AGP-1X LVDS (clock input) LVPECL (clock input) Programmable drive strength
Easy System Integration
sysIOTM Capability
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· 2.5V power supply · Hot socketing · Input pull-up, pull-down or Bus-keeper (Pin-by-pin selectable) · Open drain capability · Macrocell-based power management · IEEE 1149.1 Boundary Scan testable · IEEE 1532 compliant In-System Programmable (ISPTM)
ispMACH 5000B Introduction
The ispMACH 5000B represents the next generation of Lattice's SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance for typical designs over architectures with a lower number of inputs. In addition to the unique benefits of the SuperWIDE architecture, the ispMACH 5000B provides sysIO capability to provide support for a variety of advanced I/O standards. The ispMACH 5000B devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a single-level routing system referred to as the Global Routing Pool (GRP). Figure 1 shows the ispMACH 5000B block diagram. Together, the GLBs and the GRP allow designers to create large designs in a single device without compromising performance.
Ease of Design
· Product term sharing · Extensive clocking and OE capability · 128 to 512 macrocells · 92 to 256 I/Os · 128 to 484 pins/balls in TQFP, PQFP and fpBGA packages · Commercial and industrial temperature ranges
Broad Device Offering
Table 1. ispMACH 5000B Family Selection Guide
ispMACH 5128B Macrocells User I/O Options tPD (ns) tS Set-up with 0 Hold (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Package 128 92 3.0 1.7 2.2 275 2.5 128-pin TQFP ispMACH 5256B 256 92/144 4.0 2.1 2.7 250 2.5 128-pin TQFP 208-pin PQFP 256-ball fpBGA ispMACH 5384B 384 156/186 4.0 2.1 2.7 250 2.5 208-pin PQFP 256-ball fpBGA ispMACH 5512B 512 156/196/256 4.5 2.5 2.8 200 2.5 208-pin PQFP 256-ball fpBGA 484-ball fpBGA
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Lattice Semiconductor
Figure 1. Functional Block Diagram
I/O Bank 0
ispMACH 5000B Family Data Sheet
I/O Bank 3
VCCO0 VREF0 GCLK0
Generic Logic Block Global Routing Pool
Generic Logic Block
VCCO3 VREF3 GCLK3
TDI TDO TMS TCK
TOE
GCLK1 VCCO1 VREF1
Generic Logic Block
Generic Logic Block
GCLK2 VCCO2 VREF2 RESETB GOE1 GOE2
I/O Bank 1
I/O Bank 2
The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form groups of five product term clusters, which feed the product term sharing array and the macrocell directly. The ispMACH 5000B allows up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is designed to provide flexible clocking and control functionality with the capability to select between global, product term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell. All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing standards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide range of standards allows designers to achieve significantly higher board-level performance compared to the more traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices.
ispMACH 5000B Architecture
The ispMACH 5000B Family of In-System Programmable (ISPTM) high density programmable logic devices is based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to drive any or all of the GLBs. This mechanism allows fast, efficient connections across the entire device. Figure 1 shows the basic ispMACH 5000B architecture.
Generic Logic Block
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true and complement form for every product term. The three control product terms are used for shared reset, clock and output enable functions. 2
Lattice Semiconductor AND-Array
ispMACH 5000B Family Data Sheet
The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs from the GRP are used to form 136 lines in the AND-array (true and complement of the inputs). Each line in the array can be connected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the DualOR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset, and Shared PT OE. Every set of five product terms from the 160 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control product terms, the first, third, fourth and fifth product terms of each cluster can be used as a PTOE (output macrocells only), PT Clock, PT Preset and PT Reset, respectively. Figure 2 is a graphical representation of the AND-Array. Figure 2. ispMACH 5000B AND-Array
In[0] In[66] In[67]
PT0 PT1 PT2 PT3 PT4
Cluster 0
PT155 PT156 PT157 Cluster 31 PT158 PT159 PT160 Shared clock PT161 Shared reset PT162 Shared OE Note: Indicates programmable fuse.
Dual-OR Array
There are two OR gates per macrocell in the GLB. These OR gates are referred to as the PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate receives its five inputs from the combination of product terms associated with the product term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow logic. The PTSA OR gate receives its inputs from the combination of product terms associated with the product term cluster. Figure 3 shows the Dual-OR Array.
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