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Part: LFEC3E-3T100C
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.<<<>>>for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpga<<<>>>fabric With High-speed Dedicated Functions. Lattice S First Family to Implement This Approach is The Latticeecp-DSP<<<>>>(economy Plus DSP) Family, Providing Dedicated High-performance DSP Blocks On-chip. The Latticeec (EConomy)<<<>>>family Supports All The General Purpose Features of Latticeecp Devices Without Dedicated Function Blocks To<<<>>>achieve Lower Cost Solutions.
Company: Lattice Semiconductor Corp.
Datasheet: Download LFEC3E-3T100C datasheet File size : 64 kB
Request For quote: Find where to buy LFEC3E-3T100C
Datasheet text preview:
L
atticeECP/EC Family Handbook
J
L
atticeECP/EC Family Handbook Table of Contents
une 2004
Section I. LatticeECP/EC Family Data Sheet
Introduction
Features .... 1-1 Introduction .............. 1-2
Architecture
Architecture Overview ....... 2-1 PFU and PFF Blocks......... 2-3 Slice ....... 2-3 Routing ...... 2-6 Clock Distribution Network ...... 2-7 Primary Clock Sources............ 2-7 Clock Routing........... 2-7 sysCLOCK Phase Locked Loops (PLLs) ........ 2-8 sysMEM Memory ............ 2-10 sysMEM Memory Block......... 2-10 Bus Size Matching .......... 2-10 RAM Initialization and ROM Operation ......... 2-10 Memory Cascading ...... 2-10 Single, Dual and Pseudo-Dual Port Modes............ 2-10 Memory Core Reset .............. 2-11 sysDSP Block......... 2-12 sysDSP Block Approach Compare to General DSP ....... 2-12 sysDSP Block Capabilities .... 2-13 MULT sysDSP Element ........ 2-14 MAC sysDSP Element .......... 2-14 MULTADD sysDSP Element.......... 2-15 MULTADDSUM sysDSP Element.. 2-16 Clock, Clock Enable and Reset Resources ........... 2-16 Signed and Unsigned with Different Widths........... 2-17 OVERFLOW Flag from MAC ......... 2-17 ispLEVER Module Manager........... 2-18 Optimized DSP Functions ..... 2-18 Resources Available in the LatticeECP Family ...... 2-18 DSP Performance of the LatticeECP Family.......... 2-18 Programmable I/O Cells (PIC) ....... 2-19 PIO ....... 2-20 DDR Memory Support..... 2-24 DLL Calibrated DQS Delay Block .. 2-24 Polarity Control Logic ............ 2-26 sysIO Buffer ........... 2-26 sysIO Buffer Banks ...... 2-26 Supported Standards ............ 2-28 Hot Socketing......... 2-30 Configuration and Testing .............. 2-31 IEEE 1149.1-Compliant Boundary Scan Testability........ 2-31 Device Configuration............. 2-31 Internal Logic Analyzer Capability (ispTRACY)...... 2-31 External Resistor.... 2-31
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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T able of Contents LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Oscillator ....... 2-32 Density Shifting ...... 2-32
DC and Switching Characteristics
Absolute Maximum Ratings ............. 3-1 Recommended Operating Conditions ....... 3-1 Hot Socketing Specifications .......... 3-1 DC Electrical Characteristics............ 3-2 Supply Current (Standby) ...... 3-2 Initialization Supply Current ............. 3-3 sysIO Recommended Operating Conditions............ 3-3 sysIO Single-Ended DC Electrical Characteristics............ 3-4 sysIO Differential Electrical Characteristics ............. 3-5 LVDS ...... 3-5 Differential HSTL and SSTL.... 3-6 BLVDS ............ 3-6 LVPECL .......... 3-7 RSDS .............. 3-8 5V Tolerant Input Buffer .... 3-8 Typical Building Block Function Performance........ 3-10 Pin-to-Pin Performance (LVCMOS25 12mA Drive) ........ 3-10 Register-to-Register Performance .......... 3-10 Derating Timing Tables ... 3-11 LatticeECP/EC External Switching Characteristics......... 3-12 LatticeECP/EC Internal Timing Parameters........... 3-13 Timing Diagrams .... 3-15 PFU Timing Diagrams........... 3-15 EBR Memory Timing Diagrams...... 3-16 LatticeECP/EC Family Timing Adders .... 3-18 sysCLOCK PLL Timing ... 3-20 LatticeECP/EC sysCONFIG Port Timing Specifications .......... 3-21 JTAG Port Timing Specifications ............ 3-23 Switching Test Conditions.............. 3-24
Pinout Information
Signal Descriptions ........... 4-1 LFEC20/LFECP20 Pin Information Summary.......... 4-3 LFEC20/LFECP20 Power Supply and NC Connections ... 4-4 LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA.... 4-5
Ordering Information
Part Number Description... 5-1 Ordering Information ......... 5-1
Supplemental Information
For Further Information ..... 6-1
Section II. LatticeECP/EC Family Technical Notes
LatticeECP/EC sysIO Usage Guide
Introduction .............. 7-1 sysIO Buffer Overview ...... 7-1 Supported sysIO Standards ............. 7-1 sysIO Banking Scheme..... 7-2 VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V) ... 7-3 VCCAUX (3.3V) .......... 7-3 VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V)..... 7-3 Input Reference Voltage (VREF1, VREF2)......... 7-3 VREF1 for DDR Memory Interface .... 7-3 Mixed Voltage Support in a Bank..... 7-4 2
Others parts begin by lf
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