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Details, datasheet, quote on part number:OR2C06A
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| Part: | OR2C06A |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) |
| Description: | OR2C06A (5.0V) 15.9K Usable Gates, 576 Registers, 9K Max User RAM |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download OR2C06A datasheet File size : 3559 kB |
| Request For quote: | Find where to buy OR2C06A
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Datasheet text preview:
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Data Sheet January 2003
RCA® eries 2 Field-Programmable Gate Arrays
Features
High-performance, cost-effective, low-power 0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis) Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures Eight 3-state buffers per PFU for on-chip bus structures Fast, on-chip user SRAM has features to simplify RAM design and increase RAM speed: -- Asynchronous single port: 64 bits/PFU -- Synchronous single port: 64 bits/PFU -- Synchronous dual port: 32 bits/PFU Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU): -- 8 x 8 multiplier requires only 16 PFUs -- 30% increase in speed Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable Enhanced ascadable ibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation
Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance Upward bit stream compatible with the RCA ATT2Cxx/ ATT2Txx series of devices Pinout-compatible with new ORCA Series 3 FPGAs TTL or CMOS input levels programmable per pin for the OR2CxxA (5 V) devices Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source Built-in boundary scan (IEEE *1149.1 JTAG) and 3-state all I/O pins, (TS_ALL) testability functions Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP) Full PCI bus compliance for all devices Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ORCA Foundry Development System support (for back-end implementation) New, added features (OR2TxxB) have: -- More I/O per package than the OR2TxxA family -- No dedicated 5 V supply (VDD5) -- Faster configuration speed (40 MHz) -- Pin selectable I/O clamping diodes provide 5V or 3.3V PCI compliance and 5V tolerance -- Full PCI bus compliance in both 5V and 3.3V PCI systems
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Table 1. ORCA Series 2 FPGAs
Device OR2C04A/OR2T04A OR2C06A/OR2T06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A OR2C15A/OR2T15A/OR2T15B OR2C26A/OR2T26A OR2C40A/OR2T40A/OR2T40B Usable Gates* 4,800--11,000 6,900--15,900 9,400--21,600 12,300--28,300 15,600--35,800 19,200--44,200 27,600--63,600 43,200--99,400 # LUTs 400 576 784 1024 1296 1600 2304 3600 Registers 400 576 724 1024 1296 1600 2304 3600 Max User RAM Bits 6,400 9,216 12,544 16,384 20,736 25,600 36,864 57,600 User I/Os 160 192 224 256 288 320 384 480 Array Size 10 x 10 12 x 12 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 16 x 4 RAM (or 256 gates) per PFU.
ORCA Series 2 FPGAs
Data Sheet January 2003
Table of Contents
Contents Page Contents Page
Features ............1 Description .......3 ORCA Foundry Development System Overview .......7 Architecture ......7 Programmable Logic Cells .......7 Programmable Function Unit .........7 Look-Up Table Operating Modes ..9 Latches/Flip-Flops .....17 PLC Routing Resources .....19 PLC Architectural Description .....24 Programmable Input/Output Cells ...27 Inputs ..........27 Outputs .......28 5 V Tolerant I/O (OR2TxxB) .........29 PCI Compliant I/O ......29 PIC Routing Resources ......30 PIC Architectural Description ......31 PLC-PIC Routing Resources .......32 Interquad Routing ....34 Subquad Routing (OR2C40A/OR2T40A Only) ....36 PIC Interquad (MID) Routing .......38 Programmable Corner Cells ...39 Programmable Routing ......39 Special-Purpose Functions .........39 Clock Distribution Network ...... 39 Primary Clock ......39 Secondary Clock .......40 Selecting Clock Input Pins ..........41 FPGA States of Operation ......42 Initialization ..........42 Configuration .......43 Start-Up ......44 Reconfiguration .........44 Partial Reconfiguration .......45 Other Configuration Options .......45 Configuration Data Format .....45 Using ORCA Foundry to Generate Configuration RAM Data ..46 Configuration Data Frame ..46 Bit Stream Error Checking ......49 FPGA Configuration Modes ....49 Master Parallel Mode ..........49 Master Serial Mode ............50 Asynchronous Peripheral Mode .. 51 Synchronous Peripheral Mode ....51 Slave Serial Mode ......52 Slave Parallel Mode ............52 Daisy Chain .........53 Special Function Blocks .........54 Single Function Blocks .......54 Boundary Scan ....56 2
Boundary-Scan Instructions ........ 57 ORCA Boundary-Scan Circuitry ..58 ORCA Timing Characteristics .........62 Estimating Power Dissipation ..........63 OR2CxxA ....63 OR2TxxA .....65 OR2T15B and OR2T40B ....67 Pin Information .........68 Pin Descriptions .........68 Package Compatibility ........70 Compatibility with Series 3 FPGAs ..... 72 Package Thermal Characteristics .......128 Theta JA ....128 Theta JC ...128 Theta JC ...128 Theta JB ....128 Package Coplanarity ............129 Package Parasitics ......129 Absolute Maximum Ratings ..131 Recommended Operating Conditions .........131 Electrical Characteristics ......132 Timing Characteristics ..........134 Series 2 .....162 Measurement Conditions .....171 Output Buffer Characteristics ........172 OR2CxxA ..172 OR2TxxA ...173 OR2TxxB ...174 Package Outline Drawings ...175 Terms and Definitions .......175 84-Pin PLCC ......176 100-Pin TQFP .....177 144-Pin TQFP .....178 160-Pin QFP .......179 208-Pin SQFP ....180 208-Pin SQFP2 ........181 240-Pin SQFP ....182 240-Pin SQFP2 ........183 256-Pin PBGA ....184 304-Pin SQFP ....185 304-Pin SQFP2 ........186 352-Pin PBGA ....187 432-Pin EBGA ....188 Ordering Information ...........189
Lattice Semiconductor
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Data Sheet January 2003
ORCA Series 2 FPGAs
mable input/output cells (PICs). An array of PLCs is surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and configuration RAM. All logic is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs). The PLC architecture provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction. Some examples of the resources required and the performance that can be achieved using these devices are represented in Table 2.
Description
The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources. The Series 2 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each other. The usable gate counts associated with each series are provided in Table 1. Both series are offered in a variety of packages, speed grades, and temperature ranges. The RCA series FPGA consists of two basic elements: programmable logic cells (PLCs) and programTable 2. ORCA Series 2CA System Performance Function 16-bit loadable up/down counter 16-bit accumulator 8 x 8 parallel multiplier: -- Multiplier mode, unpipelined1 -- ROM mode, unpipelined2 -- Multiplier mode, pipelined3 32 x 16 RAM: -- Single port (read and write/ cycle)4 -- Single port5 -- Dual port6 36-bit parity check (internal) 32-bit address decode (internal)
# PFUs
Speed Grade -3 66.7 66.7 19.3 55.6 69.0 -4 87.0 87.0 25.1 71.9 82.0
Unit MHz MHz MHz MHz MHz
4 4 22 9 44
9 9 16 4 3.25
28.6 52.6 52.6 11.0 9.5
36.2 69.0 83.3 9.1 7.5
MHz MHz MHz ns ns
1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers). 4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. 6. Implemented using 16 x 2 synchronous dual-port RAM mode.
Lattice Semiconductor
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