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Details, datasheet, quote on part number:OR3T1256PS208I-DB
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Datasheet text preview:
D ata Sheet December 2002
OP
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ORCA® eries 3C and 3T Field-Programmable Gate Arrays
Features
High-performance, cost-effective, 0.35 µm (OR3C) and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 µm). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See RCA Series 3L FPGA documentation.) Up to 186,000 usable gates. Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance on OR3Txxx devices. Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU. Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement. Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and AL*like AND-OR with optional INVERT in each programma-
ble logic cell (PLC), with over 50% speed improvement typical. Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay. TTL or CMOS input levels programmable per pin for the OR3Cxx (5.0 V) devices. Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source. Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O. Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command. Programmable I/O (PIO) has: -- Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. -- Capability to (de)multiplex I/O signals. -- Fast access to SLIC for decodes and PAL-like functions. -- Output FF and two-signal function generator to reduce CLK to output propagation delay. -- Fast open-drain dive capability -- Capability to register 3-state enable signal. Baseline FPGA family used in Series 3+ FPSCs (field programmable system chips) which combine FPGA logic and standard cell logic on one device.
* PAL is a trademark of Advanced Micro Devices, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Table 1. ORCA Series 3 (3C and 3T) FPGAs
Device OR3T20 OR3T30 OR3T55 OR3C/3T80 OR3T125 System Gates 36K 48K 80K 116K 186K LUTs 1152 1568 2592 3872 6272 Registers 1872 2436 3780 5412 8400 Max User RAM 18K 25K 42K 62K 100K User I/Os 196 228 292 356 452 Array Size 12 x 12 14 x 14 18 x 18 22 x 22 28 x 28 Process Technology 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM
The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
ORCA Series 3C and 3T FPGAs
Data Sheet December 2002
Table of Contents
Contents Page Contents Page
Features.....1 System-Level Features ......4 Description .........5 FPGA Overview ..........5 PLC Logic ..........5 PIC Logic ...........6 System Features .........6 Routing .....6 Configuration .....6 ORCA Foundry Development System ............7 Architecture ........7 Programmable Logic Cells.........9 Programmable Function Unit .....9 Look-Up Table Operating Modes .....11 Supplemental Logic and Interconnect Cell (SLIC) 19 PLC Latches/Flip-Flops ...........23 PLC Routing Resources ..........25 PLC Architectural Description ..........32 Programmable Input/Output Cells.....34 5 V Tolerant I/O .........35 PCI Compliant I/O .....35 Inputs ......36 Outputs ............39 PIC Routing Resources ...........42 PIC Architectural Description ..43 High-Level Routing Resources..........45 Interquad Routing .....45 Programmable Corner Cell Routing .......46 PIC Interquad (MID) Routing ...47 Clock Distribution Network .......48 PFU Clock Sources ........48 Clock Distribution in the PLC Array ..49 Clock Sources to the PLC Array .......50 Clocks in the PICs ....50 ExpressCLK Inputs .........51 Selecting Clock Input Pins ......51 Special Function Blocks ...........52 Single Function Blocks ............52 Boundary Scan .........55 Microprocessor Interface (MPI).........62 PowerPC System ......63 i960 System .....64 MPI Interface to FPGA ............65 MPI Setup and Control ............66 Programmable Clock Manager (PCM) ....70 PCM Registers ..........71 Delay-Locked Loop (DLL) Mode ......73 Phase-Locked Loop (PLL) Mode .....74 PCM/FPGA Internal Interface ..77 PCM Operation .........77 PCM Detailed Programming ....78 PCM Applications .....81 2
PCM Cautions .......... 82 FPGA States of Operation ....... 83 Initialization ..... 83 Configuration .. 84 Start-Up .......... 85 Reconfiguration ....... 86 Partial Reconfiguration ........... 86 Other Configuration Options .. 86 Using ORCA Foundry to Generate Configuration RAM Data ...... 87 Configuration Data Frame ...... 87 Bit Stream Error Checking ...... 89 FPGA Configuration Modes..... 90 Master Parallel Mode ..... 90 Master Serial Mode ......... 1 Asynchronous Peripheral Mode ...... 92 Microprocessor Interface (MPI) Mode .......... 92 Slave Serial Mode .... 95 Slave Parallel Mode ....... 95 Daisy-Chaining ........ 96 Daisy-Chaining with Boundary Scan ..... 97 Absolute Maximum Ratings..... 98 Recommended Operating Conditions ........... 98 Electrical Characteristics......... 99 Timing Characteristics........... 101 Description ... 101 PFU Timing .. 102 PLC Timing ... 109 SLIC Timing .. 109 PIO Timing .... 110 Special Function Blocks Timing .... 113 Clock Timing .......... 121 Configuration Timing ............ 131 Readback Timing ........ 140 Input/Output Buffer Measurement Conditions........ 141 Output Buffer Characteristics......... 142 OR3Cxx ........ 142 OR3Txxx ....... 143 Estimating Power Dissipation ......... 144 OR3Cxx ........ 144 OR3Txxx (Preliminary Information) ...... 145 Pin Information........ 147 Pin Descriptions .... 147 Package Compatibility ......... 151 Compatibility with OR2C/TxxA Series .......... 152 Package Thermal Characteristics .. 195 FPGA Maximum Junction Temperature ....... 196 Package Coplanarity .... 197 Package Parasitics....... 197 Package Outline Diagrams ... 198 Terms and Definitions ........... 198 144-Pin TQFP ........ 199 Lattice Semiconductor
Data Sheet December 2002
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents Page Contents Page
208-Pin SQFP .........200 208-Pin SQFP2 .......201 240-Pin SQFP .........202 240-Pin SQFP2 .......203 256-Pin PBGA .........204 352-Pin PBGA .........205 432-Pin EBGA .........206 600-Pin EBGA .........207 Ordering Information .....208
Lattice Semiconductor
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