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Details, datasheet, quote on part number:ORSPI4-2FE1036C
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| Part: | ORSPI4-2FE1036C |
| Category: | Memory |
| Description: | QDR Memory Controller<<<>>>this QDR Memory Controller Supports Read/write Accesses to 2Mx18 Qdr-ii Memory. The Pins of This Design Are<<<>>>divided Into Two Interfaces, The Host Interface And The QDR Interface. The Host Device Accesses The QDR Memory<<<>>>through The Host Interface And CAN be External to The Orca 4 Fpga/fpsc or a Module Implemented Inside The<<<>>>orca 4 Fpga/fpsc Programmable Logic. This Design Assumes The Host Device is an External Device That<<<>>>accesses The QDR Memory Through The QDR Memory Controller Using LVTTL I/o Standard. Figure 1 Shows An<<<>>>example of How The Controller is Used When The Design is Targeted to an Orca 4 Fpsc. |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download ORSPI4-2FE1036C datasheet File size : 771 kB |
| Request For quote: | Find where to buy ORSPI4-2FE1036C
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Datasheet text preview:
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QDR Memory Controller
May 2004 Reference Design RD1019
Introduction
QDR SRAM is a new memory technology defined by a number of leading memory venders for high-performance and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate unidirectional data buses dedicated for read and write operations running at double data rate. This reference design utilizes the ORCAŽ Series 4 library elements IODDR and HIODDR to create 178MHz double data rate read/write access to the QDR memory and targets for ORCA 4 FPGA and FPSC devices.
Features
ˇ Suppor t QDR-II memory ˇ Read/Write accesses at 178 MHz double data rate with -2 ORCA 4 FPGA/FPSC ˇ 32-bit, 16-bit and 8-bit write accesses ˇ Read access parity checking ˇ Implement QDR's HSTL1 I/Os using ORCA 4 programmable I/Os, no additional HSTL buffers required ˇ Fully simulated design using memory vender's QDR simulation model
Functional Description
This QDR memory controller supports read/write accesses to 2Mx18 QDR-II memory. The pins of this design are divided into two interfaces, the host interface and the QDR interface. The host device accesses the QDR memory through the host interface and can be external to the ORCA 4 FPGA/FPSC or a module implemented inside the ORCA 4 FPGA/FPSC programmable logic. This design assumes the host device is an external device that accesses the QDR memory through the QDR memory controller using LVTTL I/O standard. Figure 1 shows an example of how the controller is used when the design is targeted to an ORCA 4 FPSC. Figure 1. System Level Support Diagram
FPSC Programmable Logic
DDR
Embedded Core
QDR Memory
DDR
QDR Memory Controller
Host Device
Double data rate allows data to be transferred on both rising and falling edges of the clock and therefore doubles the data throughput. The ORCA Series 4 FPGA/FPSC has an I/O shift register (IOSR) available for each group of four programmable I/O pads (PIOs). By proper instantiations of the IODDR/HIODDR library elements, IOSR and PIO are programmed to work together and transfer data on both clock edges. The IODDR/HIODDR library elements are on the QDR interface side. Because the host device is not in the programmable logic of the FPGA/FPSC, pipelines are added to the host interface side for increasing the total system performance. The pipelines are put into a separate module. If the host device is implemented in the programmable logic, this module may ww.latticesemi.com 1
rd1019_01
LS
attice Semiconductor
QDR Memory Controller
be removed easily. As shown in Figure 2, all signals with the "qdr" prefix are QDR interface signals, and all signals with the "host" prefix are host interface signals. The signals with an "h" prefix are the signals after or before pipeline buffering. Figure 2. Signal Names
FPGA/FPSC Programmable Logic
qdrK qdrKN qdrC qdrCN qdrRN qdrWN qdrSA qdrD qdrPD qdrBWN hostCLK hWA hRA hWD hWP hRN hWN h16 h08 hostWA hostRA hostWD hostWP hostRN hostWN host16 host08
QDR Memory
qdrCQ qdrQ qdrPQ
QDR Memory Controller Core Module
Pipeline Module
hRQ hPERR hostRQ hostPERR
Host Device
The signal summary of the design is shown in Table 1. Table 1. System Summary
ignal Name hostCLK hostWA[21:0] hostRA[21:0] hostWD[31:0] hostWP[3:0] hostRN hostWN host16 host08 hostRQ[31:0] hostPERR[3:0] qdrCQ qdrQ[15:0] qdrPQ[1:0] qdrK qdrKN qdrC qdrCN qdrRN qdrWN I/O Type I I I I I I I I I O O I I I O O O O O O I/O Standard LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL HSTL1 HSTL1 HSTL1 HSTL1 HSTL1 HSTL1 HSTL1 HSTL1 HSTL1 System clock Write address, sampled at hostCLK rising Read address, sampled at hostCLK rising Write data, sampled at hostCLK rising Write parity, sampled at hostCLK rising Read cycle indication, active low, sampled at hostCLK rising Write cycle indication, active low, sampled at hostCLK rising 16-bit access indication, active high, sampled at hostCLK rising, needs to be low for 8-bit and 32-bit access 8-bit access indication, active high, sampled at hostCLK rising, needs to be low for 16-bit and 32-bit access Read data outputs Read data parity errors, active high, bit-3 for hostRQ[31:24], bit-2 for hostRQ[23:16], bit-1 for hostRQ[15:8], bit-0 for hostRQ[7:0] Connects to QDR "Output Echo Clock" CQ Read data, connects to QDR "Data Outputs" Q Read parity, connects to QDR "Data Outputs" Q Connects to QDR "Input Clock" K Connects to QDR "Input Clock" /K Connects to QDR "Input Clock for Output Data" C Connects to QDR "Input Clock for Output Data" /C Read control, connects to QDR "Read Control Pin" /R Write control, connects to QDR "Write Control Pin" /W Function/Connection Description
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attice Semiconductor
Table 1. System Summary (Continued)
Signal Name qdrSA[19:0] qdrD[15:0] qdrPD[1:0] qdrBWN[1:0] I/O Type O O O O I/O Standard HSTL1 HSTL1 HSTL1 HSTL1
QDR Memory Controller
Function/Connection Description Address, connects to QDR "Address Inputs" SA Write data, connects to QDR "Data Inputs" D Write parity, connects to QDR "Data Inputs" D Byte write enable, active low, connects to QDR "Block Write Control Pin" /BW[1:0]
Read Access Parity Checking
The memory controller contains a parity-checking feature that will be active only during read cycles. During write cycles the values sampled on hostWD[31:0] and hostWP[3:0] will be written into the QDR memory through qdrD[15:0] and qdrPD[1:0] signals respectively. In order to make the parity checking work properly, the host device needs to generate proper hostWP[3:0] values before the writes. The values of hostPERR[3:0] signals are obtained by the XOR (exclusive OR) results of the qdrQ[15:0] and qdrPQ[1:0] data read from the QDR memory.
Floorplanning
The controller design uses two different I/O standards, HSTL1 for the QDR interface and LVTTL for the host interface. The required voltages for the design are shown in the table below.
I/O Standard HSTL1 LVTTL VDDIO (V) 1.5 3.3 VREF (V) 0.75 NA Number of I/Os Required for this Design 65 121
Because these two standards require different supply and input reference voltages, they can't be put into the same I/O bank. This design can be fit into any ORCA Series 4 FPGA or FPSC devices. For demonstration purpose, the ORSPI4 1036-ball fpSBGA package is chosen to be the target device. Figure 3 shows the available I/O banks and the number of I/Os in the banks of an ORSPI4 FPSC 1036 fpSBGA package. All HSTL1 I/Os in the design are put into I/O bank 7. Figure 3. I/O Bank Assignments
BANK 0 (TL) 96 I/Os BANK 1 (TC) 116 I/Os
BANK 7 (CL) 98 I/Os
PLC ARRAY
Used for Embedded Core I/Os
BANK 6 (BL) 112 I/Os
BANK 5 (BC) 106 I/Os
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