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Details, datasheet, quote on part number:ORT42G5FPSC
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| Part: | ORT42G5FPSC |
| Category: | Communication => Network => Network Processors |
| Description: | 1GbE PCS ip Core<<<>>>Features<<<>>>■<<<>>>Complete 1Gb Ethernet Physical Coding<<<>>>sublayer Solution Based on The ORCA<<<>>> <<<>>>ORT42G5 Device<<<>>>■<<<>>>IP Targeted to The ORT42G5 Programmable<<<>>>array Section Implements Functionality<<<>>>conforming to Ieee 803.2-2002<<<>>> Encoding/decoding For Gmii Data Octets<<<>>> Optional Auto-negotiation Function With Management<<<>>>registers And Interface<<<>>> External Gmii Interface or Internal Interface To<<<>>>single Chip Mac And PCS Implementation<<<>>>■<<<>>>Ethernet Functionality Supported BY The<<<>>>embedded Section of The ORT42G5,<<<>>>Including:<<<>>> Support For 8b/10b Encoding/decoding<<<>>> Serialization/deserialization of Code Groups For<<<>>>transmit/receive<<<>>> Clock Recovery From Encoded Data Stream |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download ORT42G5FPSC datasheet File size : 40 kB |
| Request For quote: | Find where to buy ORT42G5FPSC
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Datasheet text preview:
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1GbE PCS IP Core
May 2004 IP Data Sheet
Features
Complete 1Gb Ethernet Physical Coding Sublayer Solution Based on the ORCAź ORT42G5 Device IP Targeted to the ORT42G5 Programmable Array Section Implements Functionality Conforming to IEEE 803.2-2002
Encoding/decoding for GMII data octets Optional Auto-negotiation function with management registers and interface External GMII interface or internal interface to single chip MAC and PCS implementation
General Description
The GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA RT42G5 FPSC and provides the PCS (Physical Coding Sublayer) function. The ORT42G5 device is built on the Series 4 re-configurable embedded System-on-a-Chip (SoC) architecture and is made up of SERDES transceivers containing four channels, each operating at up to 3.7Gbps, with a full-duplex synchronous interface with built-in RX Clock and Data Recovery (CDR), and transmitter pre-emphasis, for high-speed data transmission. PCS (Physical Coding Sublayer) and PMA (Physical Media Attachment) are sublayers of the physical layer implementation of IEEE 802.3 standards. The PCS provides a uniform interface to the MAC sublayer through GMII (Gigabit Media Independent Interface) for all 1000Mb/s PHY implementations. The 1GbE PCS IP core is provided with implementation scripts, test benches and documentation.
Ethernet Functionality Supported by the Embedded Section of the ORT42G5, Including:
Suppor t for 8b/10b encoding/decoding Serialization/deserialization of code groups for transmit/receive Clock recovery from encoded data stream
Simulation Models and Test Benches Available for Free Evaluation
Block Diagram
Figure 1. 1GbE PCS Solution
ORT42G5 Device Embedded ASB Section ort42g5_inf Programmable Array Section pcs_1g_core
PLL PLL
tx/rx clocks
tx_sync SERDES 8b/10b Systembus of ORT42G5 (ASB)
tx_sm
1G Line
umi rxrxsyync_sm _ _s nc _sm rx_sync_cc
Optional autoneg
Optional Management Interface
MDIO or MAC interface
rx_sm
Optional gmii_mac_inf
GMII or MAC Interface
125MHz
Note: Optional interfaces are not needed if an Ethernet MAC Interfafce is present on-chip © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. The product described herein is subject to continuing development, and applicable specifications and information are subject to change without notice. Such specifications and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many factors, including the user's system design.
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ip1030_01
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attice Semiconductor
1GbE PCS IP Core
Functional Description
The major blocks in the GbE PCS core are shown in Figure 1. Descriptions of these blocks follow.
Transmit Section
This section implements the Transmit State Machine which is specified by Figures 36-5 and 36-6 in Clause 36 of the IEEE 802.3-2002 Standard. The PCS Transmit process continuously generates code groups based upon the TXD , TX_EN and TX_ER signals on the GMII, sending them immediately to the Line Interface. The PCS Transmit process monitors the Autonegotiation process transmit flag to determine whether to transmit data or reconfigure the link.
Receive Section
Receive Synchronization State Machine This module implements the synchronization state machine which is specified by Figure 36-9 of the IEEE 802.32002 Standard. The Synchronization process is responsible for determining whether the underlying receive channel is ready for operation. The process continuously accepts code groups from the Line Interface and scans them to detect the acquisition and maintenance of code group synchronization. This state machine also sets the sync_status flag which is monitored by the receive state machine. Receive State Machine This module implements the receive state machine, which is specified by Figures 36-7a and 36-7b in Clause 36 of the IEEE 802.3-2002 Standard. The PCS Receive process continuously accepts and monitors code-groups from the Line Interface and generates RXD , RX_DV and RX_ER on the GMII, and the internal receiving flag used by the Carrier Sense and Transmit processes.
Auto-negotiation
This module implements the auto-negotiation state machine, which is specified by the Figure 37-6 in Clause 37 of the IEEE 802.3-2002 Standard. The Auto-negotiation function that allows a device (local device) to advertise modes of operation it possesses to a device at the remote end of a link segment (link partner) and to detect corresponding operational modes that the link partner may be advertising. The Auto-negotiation function exchanges information between two devices that share a link segment and automatically configures both devices to take maximum advantage of their abilities.
Management Interface
The MDIO Management Interface is implemented based on specifications in Clause 22 of the IEEE 802.3-2002 Standard. The management interface is used to connect a management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY. The management interface consists of a pair of signals that physically transport the management information across the GMII, a frame format and a protocol specification for exchanging management frames, and a register set that can be read and written using these frames.
GMII Interface
This module, depending on the configuration, provides a GMII Interface or a connection to an on-chip MAC.
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Lattice Semiconductor ORT42G5 Interface
This section provides the following functions:
1GbE PCS IP Core
· A bridging function between the 8-bit PCS core and the 32-bit Application Specific Block (ASB). The data rate translation cross the two clock domains is achieved using asynchronous FIFOs. · Clock compensation to a tolerance of +/- 100ppm between the recovered clock and IP system clock. This is done by insertion or deletion of idle characters. · Logic to program the control registers inside the ASB through the system bus User Master Interface.
Design Parameters
Table 1. Parameter Descriptions
Parameter GMII_INF Description If this parameter is set to "yes", a GMII interface will be provided through the FPGA I/Os to an external device. If this parameter is set to "no", an internal interface will be provided to a MAC on the same chip. If this parameter is set to "yes", the Auto-negotiation module and Management registers will be enabled. If this parameter is set to "no", the Autonegotiation module and Management registers will be disabled. The optional MDIO Interface is only available if the Auto-negotiation parameter is set to "yes". If the MDIO parameter is set to "yes", an MDIO interface will be provided through the FPGA I/Os to an external device.
AUTO_NEG
MDIO_INF
Signal Descriptions
Table 2. Signal Definitions for GbE PCS Solution I/O
Signal Name Clocks and Resets RX_CLK_125 TX_CLK_125 RST_N USR_CLK GMII/MAC Interface RX_DV RX_D [7:0] RX_ER TX_ER TX_D [7:0] TX_DV MDIO Signals MDC MDIO Line Interface1 REFCLKN_A REFCLKP_A HDINN_AC HDINP_AC HDOUTN_AC HDOUTP_AC Input Input Input Input Output Output CML reference clock input SERDES Quad A CML reference clock input SERDES Quad A High-speed CML receive data input SERDES Quad A, Channel C High-speed CML receive data input SERDES Quad A, Channel C High-speed CML receive data output SERDES Quad A, Channel C High-speed CML receive data output SERDES Quad A, Channel C Input Input/Output MDIO clock MDIO bi-directional data Output Output Output Input Input Input Receive Data Valid Receive Data Bus Receive Transmit Error Indicator Transmit Data Bus Transmit Data Valid Input Input Input Input Receive Clock (125MHz) Transmit Clock (125MHz) Active Low Reset Clock for the User Master Interface Direction Description
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