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Details, datasheet, quote on part number:ORT4622BC432-DB
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| Part: | ORT4622BC432-DB |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) |
| Description: | ORT4622 (2.5V) 120K Usable Gates, 4032 Registers, 64K Max User RAM, 622Mbps Max Serial Data Rate |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download ORT4622BC432-DB datasheet File size : 1438 kB |
| Request For quote: | Find where to buy ORT4622BC432-DB
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Datasheet text preview:
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reliminary Data Sheet April 2002
ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
ntroduction
Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT4622 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.
HSI function uses Lattice's proven 622 Mbits/s serial interface core. Four-channel HSI function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 2.5 Gbits/s (full duplex). LVDS I/Os compliant with IA*-644, support hot insertion. 8:1 data multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic. On-chip phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T Recommendation G.958 (0.6 UIP-P t 250 kHz). Powerdown option of HSI receiver on a perchannel basis. Highly efficient implementation with only 3% overhead vs. 25% for 8B10B coding. In-Band management and configuration. Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks. Built-in boundry scan (IEEE 1149.1 JTAG). FIFOs align incoming data across all four channels for STS-48 (2.5 Gbits/s) operation (in quad STS-12 format). 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications.
Embedded Core Features
Implemented in an
RCA eries 3 FPGA array.
Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock, and a frame pulse. High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
* EIA is a registered trademark of Electronic Industries Association. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Table 1. ORCA ORT4622--Available FPGA Logic Device ORT4622 Usable System Gates 60K--120K Number of LUTs 4032 Number of Registers 5304 Max User RAM 64K Max User I/Os 259 Array Size 18 x 28 Number of PFUs 504
The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet April 2002
Table of Contents
Contents Page Contents Page
Introduction ...... 1 Embedded Core Features ....... 1 FPSC Highlights ........ 3 Software Support ....... 3 Description ....... 4 What Is an FPSC? ..... 4 FPSC Overview ......... 4 FPSC Gate Counting ......... 4 FPGA/Embedded Core Interface ..... 4 ORCA Foundry Development System .... 4 FPSC Design Kit ....... 5 FPGA Logic Overview ....... 5 PLC Logic ... 5 PIC Logic ... 6 System Features ....... 6 Routing ...... 6 Configuration ...... 6 More Series 3 Information .......... 6 ORT4622 Overview ......... 7 Device Layout ..... 7 Backplane Transceiver Interface ..... 7 HSI Interface ....... 9 STM Macrocell .... 9 CPU Interface ..... 9 FPGA Interface ......... 9 FPSC Configuration ........... 11 Generic Backplane Transceiver Application ...... 11 Backplane Transceiver Core Detailed Description ... 12 HSI Macro .. 12 STM Transmitter (FPGA -> Backplane) ..... 14 STM Receiver (Backplane -> FPGA) ......... 18 Powerdown Mode ..... 24 Redundancy and Protection Switching ..... 24 Memory Map .... 25 Definition of Register Types ....... 25 Memory Map Overview ..... 26 Powerup Sequencing for ORT4622 Device ..... 34 FPGA Configuration Data Format ..... 35 Using ORCA Foundry to Generate Configuration RAM Data ......... 35 FPGA Configuration Data Frame ...... 35 Bit Stream Error Checking ....... 37 FPGA Configuration Modes ..... 37 Absolute Maximum Ratings ..... 38 Recommend Operating Conditions .. 38 Electrical Characteristics ......... 39 HSI Circuit Specifications ........ 40 Input Data .. 40 Jitter Tolerance ......... 40 Generated Output Jitter ..... 40 PLL ............ 40 Input Reference Clock ....... 40 Power Supply Decoupling LC Circuit ........ 41 LVDS I/O ........... 42 LVDS Receiver Buffer Requirements ......... 43 Timing Characteristics .... 44 Description ......... 44 PFU Timing ......... 45 PLC Timing ......... 45 SLIC Timing ........ 45 PIO Timing .......... 45 Special Function Timing .... 45 Clock Timing ....... 45 Configuration Timing ......... 45 Readback Timing ..... 45 Input/Output Buffer Measurement Conditions (on-LVDS Buffer) ...... 55 FPGA Output Buffer Characteristics ....... 56 LVDS Buffer Characteristics ..... 57 Termination Resistor .......... 57 LVDS Driver Buffer Capabilities .. 57 Estimating Power Dissipation ... 58 ORT4622 Clock Power ...... 58 Pin Information .......... 59 Package Thermal Characteristics Summary .... 82 JA .......... 82 JC ............ 82 JC .......... 82 JB .......... 82 FPGA Maximum Junction Temperature ..... 82 Package Thermal Characteristics ..... 83 Package Coplanarity ....... 83 Package Parasitics .... 83 Package Outline Diagrams ...... 85 Terms and Definitions ........ 85 432-Pin EBGA ..... 86 680-Pin PBGAM ........ 87 Ordering Information ....... 88
Lattice Semiconductor
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P ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver reliminary Data Sheet April 2002
Embedded Core Features
(continued)
Pseudo-SONET protocol including A1/A2 framing. SONET scrambling and descrambling for required ones density (optional). Selected transport overhead (TOH) bytes insertion and extraction for interdevice communication via the TOH serial link.
FPSC Highlights
bined with FPGA logic to create complex functions, such as digital phase-locked loops, frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided per device. -- True internal 3-state, bidirectional buses with simple control provided by the SLIC. -- 32 x 4 RAM per PFU, configurable as single or dual port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins.
Implemented as an embedded core in the ORCA Series 3+ FPSC architecture. Allows the user to integrate the core with up to 120K gates of programmable logic (all in one device) and provides up to 242 user I/Os in addition to the embedded core I/O pins. FPGA portion retains all of the features of the ORCA Series 3 FPGA architecture: -- High-performance, cost-effective, 0.25 µm, 5-level metal technology. -- Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. -- Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU. -- Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*-like AND-OR-INVERT (AOI) in each programmable logic cell (PLC). -- Up to three ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. -- Dual-use microprocessor interface (MPI) can be used for configuration, as well as for a generalpurpose interface to the FPGA. Glueless interface to i960 and PowerPC processors with userconfigurable address space provided. -- Programmable clock manager (PCM) adjusts clock phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be com-
High-speed, on-chip interface provided between FPGA logic and embedded core to reduce bottlenecks typically found when interfacing off-chip.
Software Support
Supported by ORCA Foundry software and thirdpar ty CAE tools for implementing ORCA Series 3+ devices and simulation/timing analysis with the embedded core functions. Embedded core configuration options and simulation netlists generated by FPSC Configuration Manager utility.
* PAL is a trademark of Advanced Micro Devices, Inc. i960 is a registered trademark of Intel Corporation. PowerPC is a registered trademark of International Business Machines Corporation.
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Lattice Semiconductor
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