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Details, datasheet, quote on part number:ORT82G5-3BM680C
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| Part: | ORT82G5-3BM680C |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) |
| Description: | ORT82G5 (1.5V) 800K Usable Gates, 10368 Registers, 277K Max User RAM, 3125Mbps Max Serial Data Rate |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download ORT82G5-3BM680C datasheet File size : 3128 kB |
| Request For quote: | Find where to buy ORT82G5-3BM680C
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Datasheet text preview:
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ORCAź ORT42G5 and ORT82G5
0.6 to 3.7 Gbits/s XAUI and FC FPSCs
March 2003 Data Sheet
Introduction
Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively, each operating at up to 3.7 Gbits/s, with a full-duplex synchronous interface with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K usable FPGA system gates. The CDR circuitry available from Lattice's high-speed I/O portfolio (sysHSITM), has already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE, 10 GbE) applications. Designers can also use these devices to drive high-speed data transfer across buses within any generic system. For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can comprise a XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and protection links between a line card and switch fabric. The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel. The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5, which implements four channels of SERDES with SONET scrambling and cell processing. Table 1. ORCA ORT42G5 and ORT82G5 Family Available FPGA Logic
Device ORT42G5 ORT82G5 PFU Rows 36 36 PFU Columns 36 36 Total PFUs 1296 1296 FPGA Max. User I/O 204 372 LUTs 10,368 10,368 EBR Blocks2 12 12 EBR Bits2 (K) 111 111 FPGA System Gates (K)1 333-643 333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and four PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
Note: ORCA ORT42G5 information is preliminary.
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ORCA ORT42G5 and ORT82G5 Data Sheet
Reference Clock Requirements ........... 37 Synthesized and Recovered Clocks .... 37 Internal Clock Signals at the FPGA/Core Interface for the ORT42G5 ....... 38 Transmit and Receive Clock Rates...... 39 Transmit Clock Source Selection ......... 39 Recommended Transmit Clock Distribution for the ORT42G5 ... 39 Multi-Channel Alignment Clocking Strategies for the ORT42G5 .......... 41 Internal Clock Signals at the FPGA/Core Interface for the ORT82G5 ....... 43 Transmit and Receive Clock Rates...... 44 Transmit Clock Source Selection ......... 44 Recommended Transmit Clock Distribution for the ORT82G5 ... 45 Multi-Channel Alignment Clocking Strategies for the ORT82G5 .......... 47 Reset Operation ......... 49 Start Up Sequence for the ORT42G5 .. 50 Start Up Sequence for the ORT82G5 .. 51 Test Modes ....... 51 Loopback Testing......... 51 High-Speed Serial Loopback at the CML Buffer Interface........ 52 Parallel Loopback at the SERDES Boundary ...... 53 Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES ...... 54 SERDES Characterization Test Mode .......... 55 Embedded Core Block RAM ....... 56 Memory Maps ... 58 Definition of Register Types .. 58 ORT42G5 Memory Map........ 58 ORT82G5 Memory Map........ 67 Recommended Board-level Clocking for the ORT42G5 and ORT82G5 ........ 73 Absolute Maximum Ratings ...... 75 Recommended Operating Conditions ...... 75 SERDES Electrical and Timing Characteristics ......... 75 High Speed Data Transmitter...... 76 High Speed Data Receiver.... 77 External Reference Clock ..... 79 Embedded Core Timing Characteristics ....... 79 Pin Descriptions ......... 80 Power Supplies for ORT42G5 AND ORT82G5.......... 84 Power Supply Descriptions ... 84 Recommended Power Supply Connections........... 85 Recommended Power Supply Filtering Scheme......... 85 Package Information ........ 87 Package Pinouts .......... 87 Package Thermal Characteristics Summary 114 2
Table of Contents
Introduction ......... 1 Table of Contents......... 2 Embedded Function Features..... 4 Programmable Features .... 5 Programmable Logic System Features...... 6 Description .......... 7 What is an FPSC?.......... 7 FPSC Overview..... 7 FPSC Gate Counting ..... 7 FPGA/Embedded Core Interface ........... 7 FPSC Design Kit ............ 7 FPGA Logic Overview.... 8 PLC Logic........ 8 Programmable I/O.......... 8 Routing ... 9 System-Level Features ...... 9 Microprocessor Interface......... 9 System Bus ......... 10 Phase-Locked Loops ... 10 Embedded Block RAM .......... 10 Configuration ....... 10 Additional Information .. 11 ORT42G5/ORT82G5 Overview ......... 11 Embedded Core Overview .... 11 Serializer and Deserializer (SERDES) .......... 11 MUX/DEMUX Block ..... 12 Multi-channel Alignment FIFOs............ 12 XAUI and Fibre Channel Link State Machines ...... 12 FPGA/Embedded Core Interface ......... 12 Dual Port RAMs ........... 13 FPSC Configuration ..... 13 Backplane Transceiver Core Detailed Description .... 13 8b/10b Encoding and Decoding ........... 14 Transmit Path (FPGA to Backplane) Logic ... 16 8b/10b Encoder and 1:10 Multiplexer .. 18 CML Output Buffer ....... 18 Receive Path (Backplane to FPGA) Logic .... 19 Link State Machines..... 24 XAUI Link Synchronization Function.... 25 Multi-channel Alignment............ 27 ORT42G5 Multi-channel Alignment ..... 27 ORT82G5 Multi-channel Alignment ..... 28 XAUI Lane Alignment Function (Lane Deskew)........ 29 Mixing Half-rate, Full-rate Modes ......... 30 Multi-channel Alignment Configuration .... 30 ORT42G5 Configuration ....... 30 ORT82G5 Configuration ....... 31 ORT42G5 Alignment Sequence........... 32 ORT82G5 Alignment Sequence........... 33 Reference Clocks and Internal Clock Distribution...... 37
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JA .... 114 JC .... 115 JC .... 115 JB .... 115 FPSC Maximum Junction Temperature ...... 115 Package Thermal Characteristics ...... 115 Heat Sink Vendors for BGA Packages........ 116 Package Parasitics..... 116 Package Outline Drawings.. 117 Ordering Information ...... 118
ORCA ORT42G5 and ORT82G5 Data Sheet
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