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Details, datasheet, quote on part number:ORT8850L-1BM680I
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| Part: | ORT8850L-1BM680I |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) |
| Description: | ORT8850L (1.5V) 470K Usable Gates, 4992 Registers, 154K Max User RAM, 850Mbps Max Serial Data Rate |
| Company: | Lattice Semiconductor Corp. |
| Datasheet: | Download ORT8850L-1BM680I datasheet File size : 2781 kB |
| Request For quote: | Find where to buy ORT8850L-1BM680I
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Datasheet text preview:
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ORCA® ORT8850
Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
June 2003 Data Sheet
Introduction
Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Programmable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with highspeed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core. The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. able 1. ORCA ORT8850 Family Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)
PFU Columns 24 44 FPGA Max Total PFUs User I/Os 624 2,024 278 297 EBR Blocks 8 16 EBR Bits (K) 74 148 FPGA System Gates (K) 201 - 397 471 - 899
Device ORT8850L ORT8850H
PFU Rows 26 46
LUTs 4,992 16,192
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ort8850_03
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attice Semiconductor
ORCA ORT8850 Data Sheet
Package Thermal Characteristics Summary..... 99 JA ....... 99 JC ...... 99 JC ....... 99 JB ....... 99 FPSC Maximum Junction Temperature ...... 100 Package Thermal Characteristics ...... 100 Heat Sink Information.......... 100 Package Coplanarity .. 100 Package Parasitics......... 101 Package Outline Diagrams ..... 101 Terms and Definitions ......... 101 Package Outline Drawings.. 102 Ordering Information ...... 103
Table of Contents
Introduction ......... 1 Table of Contents......... 2 Features ..... 3 Embedded Core Features....... 3 FPGA Features ..... 4 Programmable Logic System Features.. 5 Description .......... 6 What is an FPSC?.......... 6 FPSC Overview..... 6 ispLEVER Development System............ 7 FPSC Design Kit ............ 7 FPGA Logic Overview.... 8 System-Level Features .. 9 Configuration ....... 10 Additional Information .. 10 ORT8850 Overview ......... 11 Embedded Core Overview .... 11 SONET Logic Blocks - Overview ......... 12 System Considerations for Reference Clock Distribution.... 15 SONET Bypass Mode .. 16 STM Macrocells - Overview .. 17 HSI Macrocell - Overview...... 19 Supervisory and Test Support Features - Overview ........ 19 Protection Switching - Overview .......... 21 FPSC Configuration - Overview ........... 22 Backplane Transceiver Core Detailed Description .... 25 SONET Logic Blocks, Detailed Description .. 25 Receive Path Logic ...... 34 FPGA/Embedded Core Interface Signals ......... 47 Clock and Data Timing at the FPGA/Embedded Core Interface - SONET Block ...... 49 Powerdown Mode ........ 56 Protection Switching..... 56 Memory Map ..... 57 Registers Access and General Description... 57 Electrical Characteristics........... 69 Absolute Maximum Ratings .. 69 Recommended Operating Conditions ...... 69 Power Supply Decoupling LC Circuit ... 70 HSI Electrical and Timing Characteristics ..... 71 Embedded Core LVDS I/O.... 72 Pin Information .. 76 Package Pinouts ........ 81
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L
attice Semiconductor
ORCA ORT8850 Data Sheet
Features
Embedded Core Features
· Implemented in an ORCA Series 4 FPGA. · Allows a wide range of high-speed backplane applications, including SONET transport and termination. · No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz--106 MHz clock, and a frame pulse. · High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. · Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex). · HSI function uses Lattice's 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are suppor ted. · LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes. · Low-power 1.5 V HSI core. · Low-power LVDS buffers. · Programmable STS-3, and STS-12 framing. · Independent STS-3, and STS-12 data streams per quad channels. · 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic. · On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation G.958. · Powerdown option of HSI receiver on a per-channel basis. · HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state. · Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates. · In-band management and configuration through transport overhead extraction/insertion. · Suppor ts transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted. · Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks. · Built-in boundry scan (IEEE ®1149.1 JTAG). · FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling. Optional ability to bypass alignment FIFOs. · 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices. · ORCA FPGA soft intellectual property core support for a variety of applications. · Programmable Synchronous Transport Module (STM) pointer mover bypass mode. · Programmable STM framer bypass mode. · Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface). · Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device.
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