Details, datasheet, quote on part number: PALCE22V10Z-25SC
Description24-pin ee CMOS ( Zero Power ) VersatilE PAL Device
CompanyLattice Semiconductor Corp.
DatasheetDownload PALCE22V10Z-25SC datasheet
Find where to buy


Features, Applications


x As fast as 5-ns propagation delay and 142.8 MHz fMAX (external) x Low-power EE CMOS x 10 macrocells programmable as registered or combinatorial, and active high or active low to

x Varied product term distribution allows to 16 product terms per output for complex

functions Peripheral Component Interconnect (PCI) compliant (-5/-7/-10) Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability Extensive third-party software and programmer support 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC 5-ns and 7.5-ns versions utilize split leadframes for improved performance

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The is an advanced PAL® device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed. 30 µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.

The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming EE cells to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product term disable. Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations registered output or combinatorial I/O, active high or active low (see Figure 1). The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits - S1. Multiplexer controls are connected to ground (0) through a programmable bit, selecting the "0" path through the multiplexer. Erasing the bit disconnects the control line from GND and it is driven to a high level, selecting the "1" path. The device is produced with an EE cell link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easilyimplemented programming algorithm, these products can be rapidly programmed to any customized pattern.

Variable Input/Output Pin Ratio The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND.

I/On S1 S0 Output Configuration Registered/Active Low Registered/Active High Combinatorial/Active Low Combinatorial/Active High

Registered Output Configuration Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration = 0), the array feedback is from Q of the flip-flop. Combinatorial I/O Configuration Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop 1). In the combinatorial configuration, the feedback is from the pin.


Related products with the same datasheet
Some Part number from the same manufacture Lattice Semiconductor Corp.
PALCE22V10Z-25SI 24-pin ee CMOS ( Zero Power ) VersatilE PAL Device
PALLV16V8-10JC Low Voltage, Zero Power 20-pin ee CMOS Universal Programmable Array Logic
PALLV22V10 Low-voltage Zero Power 24-pin ee CMOS VersatilE PAL Device
PLSI1032-60LG/883 High-density Programmable Logic
PLSI3256-50LG High Density Programmable Logic
PLV16V8 Low Voltage, Zero Power 20-pin ee CMOS Universal Programmable Array Logic
ip1032 Convolutional Encoder IP Core
LFEC20E-4F672C 33MHz PCI IP cores
Power1208P1 Power Manager programmable mixed-signalThe Power1208P1 device, like its predecessor the Power1208, provides a complete solution for printed circuit board (PCB) power sequencing and management through
LFXP3C-3Q208C LatticeXP FamilyFeaturesNon-volatile, Infinitely Reconfigurable• Instant-on – powers up in microseconds• No external configuration memory• Excellent design security, no bit stream tointercept•

LX128B-5F208C : IspGDX2 Family High Performance Interfacing And Switchingthe IspGDX2 Family is Lattice S Second Generation In-system Programmable Generic Digital Crosspoint Switch Forhigh Speed Bus Switching And Interface Applications.the IspGDX2 Family is Available in Two Options. The Standard De

M5-192/120-15YC : 15ns Fifth Generation Mach Architecture CPLD (Complex Programmable Logic Device)

M5-320/192-5AC : 5ns Fifth Generation Mach Architecture CPLD (Complex Programmable Logic Device)

LFXP240E7CQN208C : Latticexp2 Family Data Sheet

LCMXO2280LUTSE-3FTN256IES : Machxo Family Data Sheet

LC5256MB-4F484C : 3.3v, 2.5V and 1.8V In-system Programmable Expanded Programmable Logic Device Xpld˘â Family

LCMXO640LUTSC-4MN100CES : Machxo Family Data Sheet

LFE2M50E-6F900C : Embedded - Fpga (field Programmable Gate Array) Integrated Circuit (ics); IC FPGA 50KLUTS 410I/O 900-BGA Specifications: Number of Gates: - ; Number of I /O: 410 ; Lead Free Status: Contains Lead ; RoHS Status: RoHS Non-Compliant

LCMXO2-4000HE-4FTG256C : Embedded - Cpld (complex Programmable Logic Devices) Integrated Circuit (ics) In System Programmable; IC PLD 4320LUTS 132-CSBGA Specifications: Programmable Type: In System Programmable ; Number of Macrocells: 2160 ; Number of I /O: 105 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant

LFE2-12E-6TN144C : LatticeECP2/M Family Data Sheet The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was ac

ISPGDX80VA-3TN100 : EE PLD, 3 ns, PQFP100 Specifications: Package Type: TQFP, Other, LEAD FREE, TQFP-100 ; Logic Family: CMOS ; Pins: 100 ; Internal Frequency: 208 MHz ; User I/Os: 80 pins ; Propagation Delay: 3 ns ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 3.3V

ISPLSI2032A-110LT48 : EE PLD, 13 ns, PQCC44 Specifications: Package Type: Other, PLASTIC, LCC-44 ; Logic Family: CMOS ; Pins: 44 ; Internal Frequency: 77 MHz ; User I/Os: 32 pins ; Propagation Delay: 13 ns ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 5V

0-C     D-L     M-R     S-Z