Details, datasheet, quote on part number: LSH32
Description32-bit Cascadable Barrel Shifter
CompanyLogic Devices Inc.
DatasheetDownload LSH32 datasheet
Find where to buy


Features, Applications


The a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. It has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, including circular (barrel) shifting, left shifts with zero fill, and right shift with sign extend are possible. In addition, a built-in priority encoder is provided to aid floating point normalization. SHIFT ARRAY The 32 inputs to the LSH32 are applied a 32-bit shift array. The 32 outputs of this array are multiplexed down to 16 lines for presentation at the device outputs. The array may be configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). Alternatively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). The shift code control assignments and the resulting input to output mapping for the wrap mode are shown in Table 1. Essentially the LSH32 is configured as a left shift device. That is, a shift code of 000002 results in no shift of the input field. A code of 000012 provides an effective left shift of 1 position, etc. When viewed as a right shift, the shift code corresponds to the two's complement of the shift distance, i.e., a shift code 111112 (110) results in a right shift of one position, etc. When not in the wrap mode, the LSH32 fills bit positions for which there is no corresponding input bit. The fill value and the positions filled depend on the RIGHT/LEFT (R/L) direction pin. This pin is a don't care input when in wrap mode. For left shifts in fill mode, lower bits are filled with zero as shown in Table 2. For right shifts, however, the SIGN input is used as the fill value. Table 3 depicts the bits to be filled as a function of shift code for the right shift case. Note that the R/L input changes only the fill convention, and does not affect the definition of the shift code. In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two's complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most


u 32-bit Input, 32-bit Output Multiplexed to 16 Lines u Full 0-31 Position Barrel Shift Capability u Integral Priority Encoder for 32-bit Floating Point Normalization u Sign-Magnitude or Two's Complement Mantissa Representation u 32-bit Linear Shifts with Sign or Zero Fill u Independent Priority Encoder Outputs for Block Floating Point u 68-pin PLCC, J-Lead

significant bit a 6-bit two's complement shift code, comprised of R/L concatenated with the SI4SI0 lines. Thus a positive shift code (R/L = 0) results in a left shift of 031 positions, and a negative code (R/L 1) a right shift to 32 positions. The LSH32 can thus effectively select any contiguous 32-bit field out of a (sign extended and zero filled) 96-bit "input." OUTPUT MULTIPLEXER The shift array outputs are applied a 2:1 multiplexer controlled by the MS/LS select line. This multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. PRIORITY ENCODER The 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. The priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. Code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. Prior to the priority encoder, the input bits are individually exclusive OR'ed with the SIGN input. This allows normalization in floating point systems using two's complement mantissa representation. A negative value in two's complement representation will cause the exclusive OR gates to invert the input data to the encoder. As a result the leading significant digit will always be "1." This affects only the encoder inputs; the shift array always operates on the raw input data. The priority encoder function table is shown in Table 4.




The NORM input, when asserted results in the priority encoder output driving the internal shift code inputs directly. It is exactly equivalent to routing the SO4 SO 0 outputs back to the SI4 SI0 inputs. The NORM input provides faster normalization of 32-bit data by avoiding the delay associated with routing the shift code off chip. When using the NORM function, the LSH32 should be placed in fill mode, with the R/L input low. APPLICATIONS EXAMPLES Normalization of mantissas to 32 bits can be accomplished directly by a single LSH32. The NORM input is asserted, and fill mode and left shift are selected. The normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the MS/LS. it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two LSH32 devices can be used in parallel. Both devices receive the same input word, with the MS/LS select line of one wired high, and the other low. Each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously.


Related products with the same datasheet
Some Part number from the same manufacture Logic Devices Inc.
LSH32JC20 32-bit Cascadable Barrel Shifter
LSH33 32-bit Barrel Shifter With Registers
LT1269CT 4A High Efficiency Switching Regulators
LT4420 Dual 32 TapfIR Filter
LSI403US Ultra-sleek, extremely low-power DSPThe LSI403US is a low-cost, low-power voice processor in an ultra-thin package that delivers the perfect mix of high performance and small footprint necessary in Voice
LF3324 24Mbit Frame Buffer / FIFO FeaturesLOGIC Devices' LF3324 is the industry's largest Frame Buffer / FIFO. This next generation device incorporates 24Mbit memory with extremely flexible addressing
LF3312 12Mbit Frame Buffer / FIFOThe LF3312 is a 12,441,600 bit memory device with extremely flexible addressing capabilities along with seamless cascadability. The device's feature-set makes it ideal for DTV,
LF3304 Dual Line Buffer/FIFOThe LF3304 is a dual line buffer/FIFO,designed to operate at HDTV rates.The LF3304 will operate in two distinctmodes: Line Buffer and FIFO.In these modes the two memoriescan
LF9501 The LF9501 is a high-speed, 10-bitprogrammable line buffer. Someapplications the LF9501 is useful forinclude sample rate conversion, datatime compression/expansion, softwarecontrolled data alignment,
LF9502 The LF9502 is a high-speed, 10-bitprogrammable line buffer. Someapplications the LF9502 is useful forinclude sample rate conversion, datatime compression/expansion, softwarecontrolled data alignment,
L8C203 512/1k/2k/4k x 9-bit Asynchronous FIFO
L9D125G80BG4 2.5 Gb, DDR - Sdram Integrated Module
L8C202JC10 512/1k/2k/4k x 9-bit Asynchronous FIFO

LF3347 : High Speeddigital Image Filter With Coefficient RAM

LMA2010M-65 : 16 X 16-bitMultiplier-Accumulator

LMU216M-55 : 16 X 16-bitParallel Multiplier

LMU217M-30 : 16 X 16-bitParallel Multiplier

LT1269CT : 4A High Efficiency Switching Regulators

LF3304QC12 : Dual Line Buffer/FIFO The LF3304 is a dual line buffer/FIFO, designed to operate at HDTV rates. The LF3304 will operate in two distinct modes: Line Buffer and FIFO. In these modes the two memories can operate independently or with common control.

L8C204NI12 : 512/1k/2k/4k x 9-bit Asynchronous FIFO

L8C204NI15 : 512/1k/2k/4k x 9-bit Asynchronous FIFO

L8C203NC25 : 512/1k/2k/4k x 9-bit Asynchronous FIFO

L8C202NC25 : 512/1k/2k/4k x 9-bit Asynchronous FIFO

Same catergory

54AC151D : 8-input Multiplexer. The is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one line of data from up to eight sources. The 'AC/'ACT151 can be used as a universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. ICC reduced by 50% Outputs source/sink mA 'ACT151.

74HC11 : 74HC/HCT11; Triple 3-input And Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14).

74HC154 : 74HC/HCT154; 4-to-16 Line Decoder/demultiplexer;; Package: SOT101-1 (DIP24), SOT137 (SO24), SOT340-1 (SSOP24), SOT355-1 (TSSOP24).

HEF4020BMSI : CMOS/BiCMOS->4000 Family. 14-stage Binary Counter. For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family s HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC Product File under Integrated Circuits, IC04 January 1995 The a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully.

M54HCT241F1R : Octal Bus Buffer With 3 State Outputs Hct240: Inverted - Hct241/244 Non Inverted.

SN54AC74J : Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset. SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET EPIC TM (Enhanced-Performance Implanted CMOS) 1-m Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J,N) Packages The 'AC74 are dual positive-edge-triggered.

SN74BCT979DL : Backplane Logic (GTL, GTLP, FB/FB+, ABTE/ETL). ti SN74BCT979, 9-Bit Registered BTL Transceiver With Parity Generator/checker.

SN74LS138 : Bipolar->LS Family. 3-line to 8-line Inverting Decoder/demultiplexer.

SN74LVC1G98DBVR : Single Gates. ti SN74LVC1G98, Configurable Multiple-function Gate. Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages 5.5 V Max tpd 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 2000-V Human-Body.

SN74LVTZ245DBLE : Standard Transceivers. ti SN74LVTZ245, 3.3-V Abt Octal Bus Transceivers With 3-State Outputs.

SN75ALS170AJ : Triple Differential Bus Transceiver. Three Bidirectional Transceivers Driver Meets or Exceeds ANSI Standard EIA/TIA-422-B and RS-485 and ITU Recommendation V.11 Two Skew Limits Available Designed to Operate to 20 Million Data Transfers per Second (FAST-20 SCSI) High-Speed Advanced Low-Power Schottky Circuitry Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments.

NB7L86M : 2.5V / 3.3V 12Gb/s Differential SmartGateTM ( 2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML Outputs The NB7L86M is a multi−function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The NB7L86M is an ultra−low.

A3P060-2FG144Y : FPGA, 1536 CLBS, 60000 GATES, PBGA144. s: System Gates: 60000 ; Logic Cells / Logic Blocks: 1536 ; Package Type: Other, 13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FPBGA-144 ; Logic Family: CMOS ; Pins: 144 ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 1.5V.

AT94K05AL-25AJJ : FPGA, 256 CLBS, 5000 GATES, PQCC84. s: System Gates: 5000 ; Logic Cells / Logic Blocks: 256 ; Package Type: Other, PLASTIC, LCC-84 ; Logic Family: CMOS ; Pins: 84 ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Propagation Delay: 3.4 ns ; Supply Voltage: 3.3V.

935210570118 : LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16. s: Counter Type: BINARY COUNTER ; Counter Category: Synchronous ; Counter Direction: Bidirectional ; Supply Voltage: 1.2V, 3.6V, 2.7 ; Package Type: 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 ; Logic Family: CMOS, LVC/LCX/Z ; Number of Pins: 16 ; Number of Stages.

0-C     D-L     M-R     S-Z