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Part: 8502
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
-> Controllers
Description: Ethernet Mii to Aui Interface Adapter
Company: LSI Logic Corporation
Datasheet: Download 8502 datasheet File size : 44 kB
Request For quote: Find where to buy 8502
Datasheet text preview:
858502 02
Ethernet MII to AUI Interface Adapter
98210
Features
s Single Chip Connecting MII and AUI Interfaces s AUI Interface to Ethernet Transceiver s MII Interface to Ethernet Controller s MI Interface for Configuration & Status s Few External Components s Meets All Applicable IEEE 802.3 Standards s Interface to External E 2PROM for Automatic Preloading of MI Serial Port Bits s Many User Features and Options - Full Duplex - Powerdown - Transmitter Disable/Powerdown - Loopback - MII Disable - Link and Jabber Status Passthrough - Multiple Register Access s LED Outputs - Activity, Transmit, Receive - Collision - Link - User Programmable s 44L PLCC
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Description
The 8502 is a interface IC that provides a single chip link between an Ethernet AUI (Attachment Unit Interface) and an Ethernet MII (Media Independent Interface). The 8502 is in a 44L package. The 8502 consists of Manchester encoder, AUI transmitter, AUI receiver, Manchester decoder, Media Independent Interface (MII) to an external controller, and Management Interface (MI) serial port. The 8502 can access five 16 bit registers though the MI serial port. These registers contain configuration inputs, status outputs, and device capabilities. The 8502 is ideal for external PHY's that connect AUI or other media to MII. They are also ideal as an AUI interface to MII based Ethernet controllers in adapter cards, motherboards, and hubs.
PLED1
OSCIN
Pin Configuration
RXD1 RXD0 EE_CS EE_DI EE_CLK/XMT_LED EE_DO/RCV_LED RX_CLK RX_DV CRS COL NC 7 8 9 10 11 12 13 14 15 16 17
44
42
43
41
40
6
5
4
3
2
1
TX_EN
PLED0
GND1
RXD2
RXD3
VCC1
MDC
NC
NC
39 38 37 36 LINKI MDIO NC
8502 44L PLCC Top View
35 34 33 32 31 30 29
NC 18
DI+ 19
CI+ 21
CI 22
VCC2 23
24
DO+ 25
DO 26
NC 27
DI 20
GND2
4-1 1
MD400157/D
RBIAS
28
8502
8502 Table of Contents
1.0 Pin Description 2.0 Block Diagram 3.0 Functional Description 3.1 General 3.2 Media Independent Interface (MII) 3.2.1 General 3.2.2 MII Disable 3.3 Manchester Encoder 3.4 Manchester Decoder 3.5 AUI Transmitter 3.5.1 Transmitter 3.5.2 Transmit Activity Indication 3.5.3 Transmit Disable 3.5.4 Transmit Powerdown 3.6 AUI Receiver 3.6.1 Receiver 3.6.2 Squelch 3.6.3 Receive Activity Indication 3.7 Collision 3.7.1 General 3.7.2 Collision Detect Algorithm 3.7.3 Collision Indication 3.7.4 Collision Test 3.8 SOI (Start of Idle) 3.9 Full Duplex Mode 3.10 Loopback 3.11 Link 3.11.1 General 3.11.2 Link Algorithm 3.11.3 Link Indication 3.12 Jabber 3.13 Reset 3.14 Powerdown 3.15 Oscillator 3.16 LED Drivers 3.17 MI Serial Port 3.17.1 Signal Description 5.0 Specifications 3.17.2 Timing 3.17.3 Multiple Register Access 3.17.4 Bit Types 3.17.5 Frame Structure 3.17.6 Register Structure 3.17.7 Link Status Bit 3.17.8 Jabber Detect Bit 3.18 Register Description 3.19 External EEPROM Interface (EEI) 3.19.1 General 3.19.2 Signal Description 3.19.3 Frame Structure 3.19.4 EE_CS Cycle Structure 3.19.5 Timing 4.0 Application Information 4.1 Example Schematics 4.2 AUI Transmit Interface 4.3 AUI Receive Interface 4.4 Controller Interface 4.4.1 General 4.4.2 Output Drivers 4.4.3 MII Disable 4.5 MI Serial Port 4.5.1 General 4.5.2 Multiple Register Access 4.5.3 Serial Port Addressing 4.6 Reset 4.7 External EEPROM 4.8 Oscillator 4.9 Programmable Led Drivers 4.10 Link Passthrough 4.11 Jabber Passthrough 4.12 Power Supply Decoupling
2 4-2
MD400157/D
8502
1.0 Pin Description
Pin # 44L 8502 2 23 1 24 25 26 19 20 21 22 28 Pin Name I/O Description
VCC2 VCC1 GND2 GND1 DO+ DODI+ DICI+ CIRBIAS
-- -- O O I I I I --
Positive Supply. +5 +/-5% Volts. Ground. 0 Volts. AUI Transmit Output, Positive. AUI Transmit Output, Negative. AUI Receive Input, Positive. AUI Receive Input, Negative. AUI Collision Input, Positive. AUI Collision Input, Negative. Internal Bias Current Set. An external resistor connected between this pin and GND will create a reference current for the internal bias circuits. Clock Oscillator Input. There must be either a 20 MHz crystal or a 20 MHz clock tied between this pin and GND. TX_CLK output clock is generated from this input. Transmit Clock Output. This Media Independent Interface output provides a clock to the controller. Transmit data from the controller on TXD and TX_EN is clocked in on rising edges of TX_CLK and OSCIN. Transmit Enable Input. This Media Independent Interface input has to be asserted active high to indicate that data on TXD is valid and is clocked in on rising edges of TX_CLK and OSCIN. Transmit Data Input. These Media Independent Interface inputs contain input nibble data to be transmitted on the AUI outputs and are clocked in on rising edges of TX_CLK and OSCIN. Receive Clock Output. This Media Independent Interface output provides a clock to the controller. Receive data on RXD and RX_DV is clocked out to the controller on falling edges of RX_CLK. Carrier Sense Output. This Media Independent Interface output is asserted when valid data is detected on the AUI inputs and is clocked out on falling edges of RX_CLK. Receive Data Valid Output. This Media Independent Interface output is asserted active high when valid decoded data is present on the RXD outputs and is clocked out on falling edges of RX_CLK. Receive Data Output. These Media Independent Interface outputs contain receive nibble data from the AUI input and are clocked out on falling edges of RX_CLK.
43
OSCIN
I
30
TX_CLK
O
40
TX_EN
I
34 33 32 31 13
TXD3 TXD2 TXD1 TXD0 RX_CLK
I
O
15
CRS
O
14
RX_DV
O
3 6 7 8
RXD3 RXD2 RXD1 RXD0
O
4-3 3
MD400157/D
8502
1.0 Pin Description continued
Pin # 44L 8502 16 41 35 Pin Name I/O Description
COL MDC MDIO
O I I/O
Collision Output. This Media Independent Interface output is asserted when collision between transmit and receive data is detected. Management Interface Clock Input. This Management Interface clock shifts serial data into and out of MDIO on rising edges. Management Interface Data Input/Output. This bidirectional pin contains serial Management Interface data that is clocked in and out on rising edges of the MDC clock. Link Input. The value on this pin is either passed through to the internal MI serial port Link Status output bit In Register 1 or it enables the internal Link algorithm. 1 = Link Status Bit Is Set To 0 (Link Fail) float = Link Status Bit Determined By The Internal Link Algorithm 0 = Link Status Bit Is Set To 1 (Link Pass) In 28L 8501, the Link Status Bit is always forced to 1 (Link Pass).
36
LINKI
I Pullup To VCC/2
37
JABI
I Pullup
Jabber Input. The value on this pin is passed through to the internal MI serial port Jabber Detect output bit In Register 1. 1 0 = Jabber Detect Bit Is Set To 0 (No Jabber Detect) = Jabber Detect Bit Is Set To 1 (Jabber Detect)
In 28L 8501, the Jabber Detect Bit is always forced to 0 (No Jabber Detect). 9 EE_CS O External EEPROM Chip Select Output. During powerup or reset, this pin is a chip select output to an external EEPROM that can preload the MI serial port input bits to values other than the defaults. External EEPROM Clock Output/Transmit LED. During powerup or reset, this pin is serial data clock output to an external EEPROM that can preload the MI serial port input bits to values other than the defaults. Data is shifted in and out on EE_DI and EE_DO, respectively, on rising edges of the EE_CLK clock. During normal operation, this pin can be used as Transmit LED and can drive an LED to GND. 0 1 10 EE_DI I Pullup O = No Detect = Transmit Activity Detected, On for 50 mS
11
EE_CLK/ XMT_LED
O
External EEPROM Data Input. During powerup or reset, this pin is a data input from an external EEPROM that can preload the MI serial port input bit to values other than the defaults. External EEPROM Data Output/Receive LED. During powerup or reset, this pin is a data output to an external EEPROM that can preload the MI serial port input bit to values other than the defaults. During normal operation, this pin can be used as Receive LED and can drive an LED to GND. 0 1 = No Detect = Receive Activity Detected, On for 50 mS
12
EE_DO/ RCV_LED
4 4-4
MD400157/D
8502
1.0 Pin Description continued
Pin # 44L 8502 5 Pin Name I/O Description
PLED1 (MDA1)
I/O O.D. Pullup
Programmable LED Output/Management Interface Address Input. This pin can be programmed through the MI serial port to be either a Collision Detect output or a user select output. This pin can drive an LED from VCC. During powerup or reset, this pin is high impedance and the value on this pin is latched in as an address for the MI serial port. When programmed as Collision Detect Output: 1 = No Detect 0 = Collision Detected, On For 50 mS
4
PLED0 (MDA0)
I/O O.D. Pullup
Programmable LED Output/Management Interface Address Input. This pin can be programmed through the MI serial port to be either a Activity Detect output or a user select output. This pin can drive an LED from VCC. During powerup or reset, this pin is high impedance and the value on this pin is latched in as an address for the MI serial port. When programmed as Activity Detect Output: 1 = No Detect 0 = Activity Detected, On For 50 mS
17 18 27 29 38 39 42
NC
--
No Connect. These pins are not connected but should be tied to GND to minimize noise.
4-5 5
MD400157/D
Others parts begin by 85
85-1 85-2
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