|Category||Interface and Interconnect|
|Description||Bd4f5fs601s33 4 MA, 60 Mhz, 5-Volt Tolerant, Fail-safe I/o Buffer Datasheet 2/01|
|Company||LSI Logic Corporation|
|Datasheet||Download bd4f5fs601s33 datasheet
The bd4f5fs60ls33 bidirectional buffer cell (Figure 1) provides to 60 MHz off-chip input/output (I/O) signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic 0.13 µm process technology. One application of the bd4f5fs60ls33 buffer as a clock driver. Figure 1
60 MHz, 3.3 V I/O operation 5-Volt tolerant Fail-safe at high voltages Feedthrough protection 20 µA maximum leakage current
Minimum 4 mA current drive into 40 pF load at 60 MHz 1.8 V internal signaling for reduced power consumption Uses one standard I/O slot
The bd4f5fs60ls33 bidirectional I/O buffer contains a totem-pole type driver, a receiver, and test circuitry. Included level translation circuitry enables the driver to receive 1.8 V level signals from the ASIC circuitry
and produce 3.3 V level output at the I/O pad. Similarly, the receiver receives off-chip input at 3.3 volts and translates to 1.8 volts for the internal ASIC application. Built-in NAND-tree logic gates and IDDTN control for IDDQ leakage testing enable use of the standard LSI Logic test methodology. The buffer is 5-volt tolerant. Although the off-chip I/O signaling normally operates 3.3 V, external circuitry may cause higher voltages, typically upwards V, to appear at the chip I/O pad. Circuit and process techniques ensure that such DC or transient voltages do not damage the buffer circuitry. In the absence of a VDD supply, the buffer is fail-safe and protected against voltage feedthrough. With high voltage applied to the chip I/O pad, the buffer can survive without degradation for up to ten years. Furthermore, with a low, maximum 20 µA leakage current, the high voltage can not power up the ASIC through voltage feedthrough. The following sections describe the bd4f5fs60ls33 buffer, which adheres to the general specifications in Table 1. Table 1
Parameter Supply voltage Junction temperature Electrostatic discharge, human body model (HBM) Electrostatic discharge, charged device model (CDM) MIL-STD-883C, Method @1.5 K ESD DS5.3.1-1996 Condition Min. 0 2000 Typ. Max. Unit °C V
The final section, "System Design Guidelines", provides layout guidelines to ensure good signal integrity for applications using the noise-sensitive, high-speed cells.
Signal Direction Description EN IN Data input to driver from ASIC circuitry 0 = Normal mode 1 = Disable driver 0 = Power down entire 1 = Normal mode NAND-tree parametric test input 0 = Disable driver 1 = Normal mode Input/output pad NAND-tree parametric test output Receiver buffer output to ASIC circuitryThe following sections describe the driver side of the I/O buffer.
EN IO High Impedance High Impedance High Impedance 0 1
1. Factory IDDQ test setting 2. Don't care state, or 1
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