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Part: BDMR4103
Category:
Microprocessors
-> MIPS
Description: BDMR4103 Evaluation Board User's Guide 7/00
Company: LSI Logic Corporation
Datasheet: Download BDMR4103 datasheet File size : 261 kB
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TinyRISC® BDMR4103 Evaluation Board
User's Guide
July 2000
Order Number C14071
This document contains proprietar y information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third par ties without the express written permission of an officer of LSI Logic Corporation. Document DB15-000161-00, First Edition (July 2000). This document describes revision A of the LSI Logic Corporation TinyRISC® BDMR4103 Evaluation Board User's Guide and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, visit us at http://www.lsilogic.com. LSI Logic Cor poration reserves the right to make changes to any products described herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual proper ty rights of LSI Logic or third par ties. Copyright © 2000 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, TinyRISC, and MiniRISC are registered trademarks and SerialICE is a trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.
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Preface
This book is the primar y reference and user's guide for the TinyRISC® BDMR4103 Evaluation Board. This guide describes the basic features of the evaluation board, including hookup procedures and system configuration. For additional information that relates to the board and its components, refer to "Related Publications," on page iv.
Audience This document assumes that you are familiar with microprocessors and related suppor t devices. The people who benefit from this book are:
· ·
Organization
Engineers and managers who are evaluating the LR4103 microprocessor for possible use in a system Engineers who are designing the microprocessor into a system
This document has the following chapters:
· · · · · ·
Chapter 1, Introduction, gives an over view of the BDMR4103 Evaluation Board and describes its features. Chapter 2, Installation Procedures, explains how to connect power to the BDMR4103 Evaluation Board, go through a quick board check procedure, and install jumpers. Chapter 3, Board Design and Layout, describes the design and layout of the BDMR4103 Evaluation Board. Chapter 4, PAL Equations, provides the PAL equations for the BDMR4103 Evaluation Board. Chapter 5, Schematics, contains the schematics for the BDMR4103 Evaluation Board. Chapter 6, Bill of Materials, lists the bill of materials for the BDMR4103 Evaluation Board.
Preface
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Related Publications
TinyRISC® EZ4103 EasyMACRO Microprocessor and FBusMacro Technical Manual, LSI Logic Corporation, Order Number C14068. TinyRISC® LR4103 Microprocessor Technical Manual, LSI Logic Cor poration, Document Number DB14-000081-00. TinyRISC® BDMR4103 Evaluation Kit Getting Star ted, LSI Logic Cor poration, Document Number DB15-000095-00. MIPS PROM Monitor and C Run-Time Library User's Guide, LSI Logic Cor poration, Order Number C14017.A. The C Programming Language, 2nd edition 1988, by B Kerringhan and D. Ritchie, Prentice Hall. PC16550D Universal Asynchronous Receiver Transmitter with FIFOs, National Semiconductor Corp. Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product, Advanced Micro Devices. DS1307/DS1308 64 X 8 Serial Real Time Clock, DALLAS Semiconductor.
Conventions Used in This Manual The word asser t means to drive a signal true or active. The word deasser t means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix "0x"--for example, 0x32CF. Binar y numbers are indicated by the prefix "0b"--for example, 0b0011.0010.1100.1111. All signals with names ending in "N" are active LOW; otherwise, signals are active HIGH.
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Preface
Abbreviations The following abbreviations are used in this manual. Note that abbreviated signal names are not listed:
ASE CPLD DIMM DIN DIP DMA DRAM EDO EEPROM EJTAG EPROM FAPI FBM FET ICE ISA ISP JEDEC JTAG k Kbyte LED M Mbyte Application Specific Extension Complex Programmable Logic Device Dual Inline Memory Module Deutsches Institut für Normung Dual In-line Package Direct Memory Access Dynamic Random Access Memory Extended Data Output Electronically Erasable Programmable Read Only Memory Enhanced Joint Test Action Group Erasable Programmable Read Only Memory FBus Advanced Peripheral Interface FBusMACRO Field Effect Transistor In-Circuit Emulation Instruction Set Architecture In-System Programmable Joint Electrical Device Engineering Committee Joint Test Action Group Kilo-ohm Kilobyte Light Emitting Diode Megaohm Megabyte
Preface
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Others parts begin by bd
BD-1 BD-2 BD-3 BD-4 BD-5 BD-6 BD-7 BD-8 BD-9 BD-10 BD-11 BD-12 BD-13
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