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Details, datasheet, quote on part number:NQ80220
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Datasheet text preview:
80220/80221 80220/80221
100BASE-TX/10BASE-T Ethernet Media Interface Adapter
98184
Features
s Single Chip 100Base-TX / 10Base-T Physical Layer Solution s Dual Speed - 100/10 Mbps s Half And Full Duplex s MII Interface To Ethernet Controller s MI Interface For Configuration & Status s Optional Repeater Interface s AutoNegotiation: 10/100, Full/Half Duplex s Meets All Applicable IEEE 802.3, 10Base-T, 100Base-TX Standards s On Chip Wave Shaping - No External Filters Required s Adaptive Equalizer s Baseline Wander Correction s Interface to External 100Base-T4 PHY s LED Outputs - Link - Activity - Collision - Full Duplex - 10/100 - User Programmable s Many User Features And Options s Few External Components s Pin configuration - 44L PLCC - 80220 - 64L LQFP - 80221
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Description
The 80220/80221 are highly integrated analog interface IC's for twisted pair Ethernet applications. The 80220/ 80221 can be configured for either 100 Mbps (100BaseTX) or 10 Mbps (10Base-T) Ethernet operation. The 80220 is packaged in a 44L package, while the 80221 is packaged in a 64L package and contains a few more features. The 80220/80221 consist of 4B5B/Manchester encoder/ decoder, scrambler/descrambler, 100Base-TX/10Base-T twisted pair transmitter with wave shaping and output driver, 100Base-TX/10Base-T twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, AutoNegotiation, controller interface (MII), and serial port (MI). The addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external filters normally required in 100Base-TX and 10Base-T applications. The 80220/80221 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip AutoNegotiation algorithm. The 80220/80221 can access eleven 16-bit registers though the Management Interface (MI) serial port. These registers contain configuration inputs, status outputs, and device capabilities. The 80220/80221 are ideal as media interfaces for 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs, and external PHY's.
4-1 1
MD400159/E
80220/80221
PLED1 (MDA1)
Pin Configuration
PLED0 (MDA0)
GND2
VCC2
GND1 41
VCC1
44
43
42
40
6
5
4
3
2
1
REXT
TPO+
TPO-
TPI+
TPI-
PLED2 (MDA2) PLED3 (MDA3) GND3 VCC3 VCC4 MDINT (MDA4) MDC MDIO COL CRS RX_DV
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36
TRFADJ0 TRFADJ1 OSCIN GND4 TX_EN TX_ER / TXD4 TXD3 TXD2 TXD1 TXD0 TX_CLK
80220 TOP VIEW 44L PLCC
35 34 33 32 31 30 29
RX_ER / RXD4 18
VCC5 24
RXD3 19
RXD2 20
RXD1 21
RXD0 22
GND5 23
RX_EN / JAM 26
GND6 27
PLED1 (MDA1)
PLED0 (MDA0)
PLED5
GND2
RX_CLK 25
GND1
VCC6 28
VCC2
VCC1
TPO
TPI+
REXT 50
TPO+
TPI
NC
NC
NC
63
61
59
57
51
64
62
60
58
56
55
54
53
52
49
NC
NC PLED4 PLED2 (MDA2) PLED3 (MDA3) NC GND3 VCC3 VCC4 MDINT (MDA4) MDC MDIO COL CRS RX_DV NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RX_ER / R4D4 18 RXD3 19 NC 17 RXD1 21 RXD0 22 GND5 23 24 VCC5 25 RX_CLK 26 RX_EN / JAM 27 T4OE 29 T4ADV 30 GND6 31 VCC6 32
48 47 46 45 44 43
NC NC TRFADJ0 TRFADJ1 NC NC OSCIN GND4 TX_EN TX_ER / TXD4 TXD3 TXD2 TXD1 TXD0 TX_CLK NC
80221 TOP VIEW 64L LQFP
42 41 40 39 38 37 36 35 34 33
RXD2 20
2
MD400159/E
T4LINK 28
RPTR
80220/80221
80220 / 80221 TABLE OF CONTENTS 1.0 Pin Description 2.0 Block Diagram 3.0 Functional Description
3.1 General 3.2 Differences between 80220 and 80221 3.3 Controller Interface 3.3.1 General 3.3.2 MII - 100 Mbps 3.3.3 MII - 10 Mbps 3.3.4 FBI - 100 Mbps 3.3.5 Selection of MII or FBI 3.3.6 MII Disable 3.3.7 Receive Output High Impedance Control 3.3.8 TXEN to CRS Loopback Disable 3.4 Encoder 3.4.1 4B5B Encoder - 100 Mbps 3.4.2 Manchester Encoder - 10 Mbps 3.4.3 Encoder Bypass 3.5 Decoder 3.5.1 4B5B Decoder 3.5.2 Manchester Decoder 3.5.3 Decoder Bypass 3.5 Clock and Data Recovery 3.5.1 Clock Recovery - 100 Mbps 3.5.2 Data Recovery - 100 Mbps 3.5.3 Clock Recovery - 10 Mbps 3.5.4 Data Recovery - 10 Mbps 3.6 Scrambler 3.6.1 100 Mbps 3.6.2 10 Mbps 3.6.3 Scrambler Bypass 3.7 Descrambler 3.7.1 100 Mbps 3.7.2 10 Mbps 3.7.3 Descrambler Bypass 3.8 Twisted Pair Transmitter 3.8.1 100 Mbps 3.8.2 10 Mbps 3.8.3 Transmit Level Adjust 3.8.4 Transmit Rise and Fall Time Adjust 3.8.5 STP (150 Ohm) Cable Mode 3.8.6 Transmit Activity Indication 3.8.7 Transmit Disable 3.8.8 Transmit Powerdown 3.9 Twisted Pair Receiver 3.9.1 Receiver - 100 Mbps 3.9.2 Receiver - 10 Mbps 3.9.3 TP Squelch - 100 Mbps 3.9.4 TP Squelch - 10 Mbps 3.9.5 Equalizer Disable 3.9.6 Receive Level Adjust 3.9.7 Receive Activity Indication 3.10 Collision 3.10.1 100 Mbps 3.10.2 10 Mbps 3.10.3 Collision Test 3.10.4 Collision Indication 3.11 Start of Packet 3.11.1 100 Mbps 3.11.2 10 Mbps 3.12 End of Packet 3.12.1 100 Mbps 3.12.2 10 Mbps 3.13 Link Integrity & AutoNegotiation 3.13.1 General 3.13.2 10BaseT Link Integrity Algorithm - 10 Mbps 3.13.3 100BaseTX Link Integrity Algorithm - 100 Mbps 3.13.4 AutoNegotiation Algorithm 3.13.5 AutoNegotiation Outcome Indication 3.13.6 AutoNegotiation Status 3.13.7 AutoNegotiation Enable 3.13.8 AutoNegotiation Reset 3.13.9 Link Indication 3.13.10 Link Disable 3.13.11 100BaseT4 Capability 3.14 Jabber 3.14.1 100 Mbps 3.14.2 10 Mbps 3.14.3 Jabber Disable 3.15 Receive Polarity Correction 3.15.1 100 Mbps 3.15.2 10 Mbps 3.15.3 Autopolarity Disable 3.16 Full Duplex Mode 3.16.1 100 Mbps 3.16.2 10 Mbps 3.16.3 Full Duplex Indication 3.17 100 / 10 Mbps Selection 3.17.1 General 3.17.2 100 / 10 Mbps Indication
4-3 3
MD400159/E
80220/80221
80220 / 80221 TABLE OF CONTENTS continued
3.18 Loopback 3.18.1 Internal CRS Loopback 3.18.2 Diagnostic Loopback 3.19 Automatic JAM 3.19.1 100 Mbps 3.19.2 10 Mbps 3.20 Reset 3.21 Powerdown 3.22 Oscillator 3.23 LED Drivers 3.24 100Base-T4 Interface 3.25 Repeater Mode 3.26 MI Serial Port 3.26.1 Signal Description 3.26.2 Timing 3.26.3 Multiple Register Access 3.26.4 Bit Types 3.26.5 Frame Structure 3.26.6 Register Structure 3.26.7 Interrupt 5.8 FBI Controller Interface 5.9 Repeater Applications 5.9.1 MII Based Repeaters 5.9.2 Non-MII Based Repeaters 5.9.3 Clocks 5.10 Serial Port 5.10.1 General 5.10.2 Polling vs. Interrupt 5.10.3 Multiple Register Access 5.10.4 Serial Port Addressing 5.11 Long Cable 5.12 Automatic JAM 5.13 Oscillator 5.14 Programmable LED Drivers 5.15 Power Supply Decoupling
6.0 Specifications 7.0 Ordering Information
7.1 44 Pin PLCC 7.2 64 Pin LQFP
4.0 Register Description 5.0 Application Information
5.1 Example Schematics 5.2 TP Transmit Interface 5.3 TP Receive Interface 5.4 TP Transmit Output Current Set 5.5 Cable Selection 5.6 Transmitter Droop 5.7 MII Controller Interface 5.7.1 General 5.7.2 Clocks 5.7.3 Output Drive 5.7.4 MII Disable 5.7.5 Receive Output Enable
8.0 Package Diagrams
8.1 44 Pin PLCC 8.2 64 Pin LQFP
9.0 Addendum
4
MD400159/E
80220/80221
1.0 Pin Description
Pin Name 44L 64L 28 24 11 10 1 44 27 23 36 9 4 41 42 43 2 3 40 37 29 32 25 8 7 57 56 31 23 41 6 60 52 54 55 58 59 50 42 34 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 GND6 GND5 GND4 GND3 GND2 GND1 TPO+ TPO TPI+ TPI REXT OSCIN TX_CLK Pin# I/O -- Description Positive Supply. 5 ± 5% Volts
--
Ground. 0 Volts
O O I I -- I O
Twisted Pair Transmit Output, Positive. Twisted Pair Transmit Output, Negative. Twisted Pair Receive Input, Positive. Twisted Pair Receive Input, Negative. Transmit Current Set. An external resistor connected between this pin and GND will set the output current level for the twisted pair outputs. Clock Oscillator Input. There must be either a 25 Mhz crystal between this pin and GND or a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input. Transmit Clock Output. This controller interface output provides a clock to an external controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on rising edges of TX_CLK and OSCIN. Transmit Enable Input. This controller interface input has to be asserted active high to indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK and OSCIN. Transmit Data Input. These controller interface inputs contain input nibble data to be transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN when TX_EN is asserted. Transmit Error Input. This controller interface input causes a special pattern to be transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising edges of TX_CLK when TX_EN is asserted. If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the fifth TXD transmit data input, TXD4.
35
40
TX_EN
I
33 32 31 30 34
38 37 36 35 39
TXD3 TXD2 TXD1 TXD0 TX_ER / TXD4
I
I
25
26
RX_CLK
O
Receive Clock Output. This controller interface output provides a clock to an external controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of RX_CLK. Carrier Sense Output. This controller interface output is asserted active high when valid data is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK. Receive Data Valid Output. This controller interface output is asserted active high when valid decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK. Receive Data Output. These controller interface outputs contain receive nibble data from the TP input, and they are clocked out on falling edges of RX_CLK.
16 17 19 20 21 22
13 14 19 20 21 22
CRS RX_DV RXD3 RXD2 RXD1 RXD0
O O O
4-5 5
MD400159/E
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