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Details, datasheet, quote on part number:NQ80C25
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| Part: | NQ80C25 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) |
| Description: | Autoduplex CMOS Ethernet Interface Adapter in 28L Package Manual 12/96 |
| Company: | LSI Logic Corporation |
| Datasheet: | Download NQ80C25 datasheet File size : 335 kB |
| Request For quote: | Find where to buy NQ80C25
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Datasheet text preview:
Full Duplex
AutoDUPLEXTM CMOS Ethernet Interface Adapter in 28L Package
96345
8080C25 C25
Functional Features
s Low Power CMOS Technology Ethernet Serial Interface Adapter with Integrated Manchester Code Converter (MCCTM), AUI and 10Base-T Transceiver with Output Wave Shaping and on chip filters. s Meets IEEE 802.3 10Base-5, 10Base-2, 10Base-T Standards s Direct Interface to SEEQ & INTEL Controllers, See the 80C26 Data Sheet for Direct Interface to AMD and NSC Controllers s Automatic or Manual Selection of AUI/10Base-T Interface s Provides AutoDUPLEXTM Detect Function for SEEQ LAN Controllers, Doubling Bandwidth to 20 MBits/sec for Switched Networks s Separate Analog/Digital Power and Ground Pins to Minimize Noise
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Interface Features
s Meets IEEE 10Base-T Standards and IEEE 802.3 standards for AUI. s On Chip Transmit Wave Shaping and Low Pass Filter Circuits - No External Filters Required s Link Integrity Test Disable, Selectable Coded Link Pulse for AutoDUPLEX Mode s Automatic Polarity Correction s Low differential and common mode noise on TP transmit outputs. s Differential Transmit Drivers to support 50 Meters of AUI Cable Lengths.
Pin Configuration
TP/AUI
28 GND 1
FDPLX
26 REXT
DO +
s Direct AUI interface to the Manchester Code Converter.
VCC1
CIS
General Description
25 24 23
27
4
3
2
1
DO CI + CI DI + DI
5 6 7 8 9
TPO + TPO TPI + TPI TXEN TXD RXD
28 Pin PLCC Top View
22 21 20 19
LNK_LED/LNK_DIS 10 FDPLX_DET 11
The SEEQ 80C25 is a CMOS single chip Ethernet serial interface adapter with a integrated Manchester Code Converter (MCC), AUI & 10Base-T transceiver with wave shaping & filters eliminating the need for external filters. The 80C25 is designed to interface directly with SEEQ and Intel Ethernet data link controllers. The chip provides automatic polarity correction, automatic port selection, separate analog & digital ground pins & a link disable feature. It also provides a selectable coded link pulse to implement AutoDUPLEX function together with SEEQ family of controllers allowing seamless full duplex operation in switched network implementations doubling network bandwidth to 20 Mbps in 10Base-T. The 80C25 is typically suitable for adapter boards, motherboards and stand-alone TP transceiver designs & switching hubs.
VCC2 15
12
TXC 13
COL 14
GND 2 16
X1 17
CSN
MCC and AutoDUPLEX are trademarks of SEEQ Technology, Inc.
RXC
18
1
MD400142/D
80C25
80C25 Pin Description
Pin 1 2 Name VCC1 TP/AUI I/O -- I Pullup To VCC/2 Description Power Supply. +5 Volts. TP or AUI or Autoport Select Input. This pin selects the interface to the ENDEC. This pin is a three state input that is internally biased at VCC/2. TP/AUI 1 float 0 3 CIS I Pulldown TP Port Autoport AUI Port
Controller Interface Select Input.
CIS 0 1 SEEQ Intel
The 80C26 Provides interface to NSC and AMD Controllers. 4 5 6 7 8 9 10 DO + DO CI + CI DI + DI LNK_LED /LNK_DIS O O I I I I I/O AUI Transmit Output, Positive. AUI Transmit Output, Negative. AUI Collision Input, Positive. AUI Collision Input, Negative. AUI Receive Input, Positive. AUI Receive Input, Negative. Link Detect Output and Link Disable Input. This pin consists of an open drain output transistor. If the pin is tied to DGND, the link test function is disabled. Otherwise, the pin is a Link Pulse Detect output and can drive an LED. LNK_LED = 1 Output Link Pulse Not Detected LNK_LED = 0 LNK_LED = DGND 11 FDPLX_DET O Output Input Link Pulse Detected Link Test Function Disabled
Full Duplex Detect Output. When FDPLX_DET = 0, the device has been placed in the full duplex mode by either selection or by the AutoDUPLEX feature. Carrier Sense Output. This controller interface output indicates valid data and collisions on the receive TP or AUI inputs. Transmit Clock Output. This controller interface output provides a 10 MHz clock to the controller. Transmit data from the controller on TXD is clocked in on edges of TXC.
12 13
CSN TXC
O O
2
MD400142/D
80C25
Pin Description cont'd
Pin 14 15 16 17 Name COL VCC2 GND2 X1 I/O O -- -- I Description Collision Output. This controller interface output is asserted when collision transmit and receive data occurs and during SQE test. Power Supply. +5 Volts. Ground. 0 Volts. Crystal Oscillator Input. The master clock for the device is generated by either placing a crystal between X1 and DGND, or by applying an external clock to X1. If a crystal is used as the clock source, connect a 1M resistor between X1 and GND. For external oscillator operation, connect a 470 resistor in series between X1 and clock source. 18 RXC O Receive Clock Output. This controller interface output provides a 10 MHz clock to the controller. Receive data on RXD is clocked out on edges of RXC. Receive Data Output. This controller interface output contains receive data decoded from the receive TP/AUI inputs and is clock out on edges of RXC. Transmit Data Input. This controller interface input contains data to be transmitted on either TP or AUI transmit outputs and is clocked in on edges of TXC. Transmit Enable Input. This controller interface input has to be asserted when data on TXD is valid. Twisted Pair Receive Input, Negative. Twisted Pair Receive Input, Positive. Twisted Pair Transmit Output, Negative. Twisted Pair Transmit Output, Positive. Transmit Current Set. An external resistor tied between this pin and AGND sets the twisted pair transmit output current level on TPO±. Full Duplex/AutoDUPLEX Mode Select Input. This pin is a three state input that is internally biased to VCC/2. FDPLX 1 float 0 28 GND1 -- Full Duplex Mode AutoDUPLEX Mode Normal
19
RXD
O
20
TXD
I
21 22 23 24 25 26 27
TXEN TPI TPI+ TPO TPO+ REXT FDPLX
I I I O O -- I Pullup to VCC/2
Ground. 0 Volts.
3
MD400142/D
80C25
BLOCK DESCRIPTION Functional Description
The 80C25 is an Ethernet adapter with a integrated Manchester Code Converter, 10Base-T transceiver with on chip filters. The device contains both 10Base-T and AUI interfaces compliant with IEEE 802.3 specifications. The chip is divided into four major blocks, namely (i) The controller interface (ii) The Encoder / Decoder (iii) The twisted pair interface and (iv) The AUI. The input signals are received on the TP or AUI receivers depending on which is selected. Both the twisted pair and AUI receivers contain a threshold comparator to validate the signal and a zero crossing comparator for checking the transitions. Then the data is sent to the PLL in the decoder to separate the data from the clock. On the other side, digital transmit data is clocked into the device via the controller interface. The data is then sent to the Manchester encoder to be encoded. Encoded data is then transmitted on the twisted pair or AUI based on the selected port.
The Encoder/Decoder
Manchester encoding is a process of combining the clock & the data stream together so that they can be transmitted on the twisted pair interface or AUI at the transceiver side. Once encoded, the first half contains the complement of the data and the second half contains the true data, so that a transition is always guaranteed at the middle of a bit cell. Data encoding and transmission begins with TXEN going active, and the subsequent data is clocked on the edges of TXC and then gets encoded. The end of a transmit packet occurs at a bit cell center if the last bit is a "ONE" or at a bit boundary if the last bit is a "ZERO". The decoding is a process of recovering the encoded data stream coming from the receiver side and decoding it back into the clock and data outputs using the phase locked loop technique. The PLL is designed to lock into the preamble of the incoming signal at less than 15 bit times with a maximum jitter of ±13.5 ns at the TPI or AUI inputs and can also sample the incoming data with this amount of jitter. The ENDEC asserts the CSN signal to indicate to the controller that the data and clock received are valid and available. There is an inhibit period after the end of a frame after a node has finished transmitting for 4.4 µs during which CSN is deasserted irregardless of the state of the receiver and collision status.
The Controller Interface
The 80C25 is designed to interface directly to all of SEEQ's Ethernet controllers, and INTEL's 82586/596/592/593 LAN controllers, with the use of CIS Pin. The controller interface consists of the Transmit/Receive data (TXD/ RXD), transmit/receive Clocks (TXC/RXC), the Transmit Enable (TXEN) input, the collision output (COLL), the Full Duplex acknowledgment (FDPLX_DET) and the Carrier Sense Output (CSN) pins. On the transmit side, data on TXD is clocked into the device on the edges of TXC clock output only when the data valid signal (TXEN) is asserted. On the receive side, data on RXD is clocked out on edges of RXC. In the SEEQ mode, RXC follows TXC for 1.5 µs and then switches to the recovered clock. In the Intel mode, RXC is held low for 1.5 µs while the PLL is acquiring lock and then switches to the recovered lock. The FDPLX_DET pin signifies to the controller that full duplex channels have been established.
Twisted Pair Interface
(a) The transmitter function The transmitter transfers Manchester encoded data from the ENDEC to the twisted pair cable. The circuit consists of a set of functional blocks to provide pre-coded waveshaped, pre-equalized and smoothed waveforms so that the outputs are made to appear as though it had passed through a 5-7th order external elliptic passive filter, thereby eliminating the need for an external filter. The waveform generator consists of a ROM, DAC, PLL, filter and a output driver to preshape the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE STD 802.3 and illustrated in figure 12. The DAC first converts the data pulse into a stair stepped representation of the desired output waveform, which goes through a second order low-pass filter. The DAC values are determined from the ROM addresses, which are chosen to have different values for long and short data bits so as to shape the pulse to meet the 10Base-T waveform template. The line driver takes the smoothed current waveform and converts it into an high current output that can drive the TP directly without any external filters. The current output is guaranteed to have a
The 80C25 supports SEEQ and INTEL Controllers according to Table 1.
Table 1. CIS Pin Description CIS 0 1 Controller Interface SEEQ INTEL
4
MD400142/D
+
TX
TX+
X1
OSCILLATOR
JABBER DETECT
ENDEC
RX+ RX
TXD
TXEN
MANCHESTER ENCODER AUI SQUELCH CONTROLLER INTERFACE
RECEIVE DATA
TRANSMIT DATA
CSN Vth COLLISION DATA
MANCHESTER DECODER (PLL)
RXD
COLL
COLLISION DETECT TP INTERFACE + DAC LP FILTER
ROM
TP/AUI
CIS
FDPLX
CLOCK GEN (PLL)
AUTO DUPLEX DETECT
FDPLX_DET
MODE INPUTS AND OUTPUTS SOI GEN
LNK_LED/LNK_DIS
PORT DETECT
V C1 C
LINK PULSE DETECT
POLARITY DETECT
GND 1
V C2 C
GND 2
TP SQUELCH +
80C25
Figure 1. 80C25 Block Diagram
+ +
LINK PULSE DETECT
+ +
+
RXC
+ +
CI+ CI +/Vth
MD400142/D
SOI DETECT
Vth REXT TPO+ TPO
TXC
5
LP FILTER
TPI+ TPI
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