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Details, datasheet, quote on part number:NQ84220
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| Part: | NQ84220 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) |
| Description: | Quad 10/100 MBPS TX/FX/10BT (PHY) Manual 2/99 |
| Company: | LSI Logic Corporation |
| Datasheet: | Download NQ84220 datasheet File size : 1435 kB |
| Request For quote: | Find where to buy NQ84220
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Datasheet text preview:
s M
842 0 842220
Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device
99036
Features
s Single Chip 100BaseTX/100BaseFX/10BaseT Physical Layer Solution
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Four Independent Channels in One IC
s 3.3V Power Supply with 5V Tolerant I/O s Dual Speed - 10/100 Mbps s Half and Full Duplex s MII Interface or Reduced Pin Count MII (RMII) Interface to Ethernet Controller s MI Interface for Configuration and Status s Optional Repeater Interface s AutoNegotiation for 10/100, Full/Half Duplex s Meets all Applicable IEEE 802.3, 10BaseT, 100BaseTX and 100BaseFX Standards s On Chip Wave Shaping - No External Filters Required s Adaptive Equalizer for 100BaseTX s Baseline Wander Correction s LED Outputs Link Activity Collision Full Duplex Far End Fault (for FX) 10/100 s160L PQFP
Description
The 84220 is a highly integrated Ethernet Transceiver for twisted pair and fiber Ethernet applications. The 84220 can be configured for either 100 Mbps (100BaseFX or 100BaseTX) or 10 Mbps (10BaseT) Ethernet operation. The 84220 consists of four (4) separate and independent channels. Each channel consists of: 4B5B/Manchester encoder, scrambler, transmitter with wave shaping and onchip filters, transmit output driver, receiver with adaptive equalizer, filters, baseline wander correction, clock and data recovery, descrambler, 4B5B/Manchester decoder, and controller interface (MII or RMII). The addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external filters normally required in 100BaseTX and 10BaseT applications. The 84220 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation, for each channel independently, using the on-chip AutoNegotiation algorithm. The 84220 can access eleven 16-bit registers for each channel through the Management Interface (MI) serial por t. These registers comply to Clause 22 of IEEE 802.3u and contain configuration inputs, status outputs, and device capabilities. The 84220 is ideal as a media interface for 100BaseTX/ 100BaseFX/10BaseT switching hubs, repeaters, routers, bridges, and other multi port applications. The 84220 is implemented in a low power CMOS technology and operates with a 3.3V power supply.
1
D400177/B
PHYAD4
PHYAD3
PHYAD2
LED2_0
LED1_0
LED0_0
LED2_1
LED1_1
LED0_1
LED2_2
LED1_2
LED0_2
LED2_3
LED1_3
LED0_3
RXCLK_0
RXDV_0
TXD3_0
TXD2_0
TXD1_0
TXD0_0
CRS_0 VDD VDD
GND VDD JAM GND GND GND 9 8 7 6 4 3 2 1 5 39 16 15 14 13 12 11 10 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
TXER_0/TXD4_0
TXCLK_0
RXER_0/RXD4_0
TXEN_0
RXD0_0
RXD1_0
RXD2_0
RXD3_0
COL_0
VDD 40
1.0 Pin Configuration
MD400177/B
VDD 41 42 RXD3_1 RXD2_1 43 RXD1_1 44 RXD0_1 45 RXDV_1 46 RXCLK_1 47 RXER_1/RXD4_1 48 TXER_1/TXD4_1 49 TXCLK_1 50 TXEN_1 TXD0_1 TXD1_1 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TXD2_1 TXD3_1 GND COL_1 CRS_1 GND VDD RXD3_2 RXD2_2 RXD1_2 RXD0_2 RXDV_2 RXCLK_2 52 51 160 GND 159 SD_THR 158 TPIP_0/FXOP_0 157 TPIN_0/FXON_0 156 SD_0/FXEN_0 155 154 TPOP_0/FXIN_0 VDD 153 GND 152 TPON_0/FXIP_0 151 VDD 150 GND 149 SD_1/FXEN_1 148 TPON_1/FXIP_1 147 VDD 146 GND 145 TPOP_1/FXIN_1 144 VDD 143 TPIN_1/FXON_1 142 TPIP_1/FXOP_1 141 GND 140 REXT 139 TPIP_2/FXOP_2 138 TPIN_2/FXON_2 137 SD_2/FXEN_2 136 TPOP_2/FXIN_2 135 VDD 134 GND 133 TPON_2/FXIP_2 132 VDD 131 GND 130 SD_3/FXEN_3 129 TPON_3/FXIP_3 128 VDD 127 GND 126 TPOP_3/FXIN_3 125 VDD 124 TPIN_3/FXON_3 123 TPIP_3/FXOP_3 122 GND 121 GND
84220 160 Pin PQFP Top View 84220 160 Pin PQFP Top View
2
TXER_2/TXD4_2 TXCLK_2 TXEN_2 TXD0_2 TXD1_2 TXD2_2 TXD3_2 COL_2 CRS_2 GND VDD RXD3_3 RXD2_3
RXER_2/RXD4_2
109
107 VDD
108 GND
111 ANEG
118 CLKIN
114 LED3_0
115 LED3_1
116 LED3_2
117 LED3_3
105 DPLX_1
106 DPLX_0
104 DPLX_2
110 LEDDEF
84220
112 SPEED_0
113 SPEED_1
119 SPEED_2
120 SPEED_3
81 RXD1_3 RXD0_3 RXDV_3 RXCLK_3
82
83
84
85 RXER_3/RXD4_3
86 TXER_3/TXD4_3
87 TXCLK_3
88 TXEN_3
89 TXD0_3
90 TXD1_3
91 TXD2_3
92 TXD3_3
93 COL_3
100 VDD
103 DPLX_3
101 RMII_EN
102 REPEATER
94 CRS_3
95 GND
96 VDD
97 MDIO
98 MDINT
99 MDC
RESET
84220
1.0 PIN DESCRIPTION
Power Supplies
Pin # 15 16 22 40 41 60 78 96 100 107 125 128 132 135 144 147 151 154 7 14 21 39 56 59 77 95 108 121 122 127 131 134 141 146 150 153 160 Pin Name VDD I/O --Description Positive Supply. +3.3 +/-5% Volts.
GND
---
Ground. 0 Volts.
3
MD400177/B
1
T
84220
1.0 PIN DESCRIPTION (cont'd)
Media Interface
Pin # 126 136 145 155 29 133 148 152 23 139 142 158 24 138 143 157 130 137 149 156 Pin Name TPOP_[3:0]/ FXIN_[3:0] I/O I/O Description Twisted Pair Transmit Output, Positive. Fiber Receive Input, Negative.
TPON_[3:0]/ FXIP_[3:0]
I/O
Twisted Pair Transmit Output, Negative. Fiber Receive Input, Positive.
TPIP_[3:0]/ FXOP_[3:0]
I/O
Twisted Pair Receive Input, Positive. Fiber Transmit Output, Positive.
TPIN_[3:0]/ FXON_[3:0]
I/O
Twisted Pair Receive Input, Negative. Fiber Transmit Output, Negative.
SD_[3:0]/ FXEN_[3:0]
I
Fiber Interface Signal Detect Input. Fiber Interface Enable. When this pin in not tied to GND, the fiber interface is enabled and this pin becomes a Signal Detect ECL input. The trip point for this ECL input is determined by the voltage applied to the SD_THR pin. When this pin is tied to GND, the fiber interface is disabled (i.e. TP Interface is enabled). Fiber Interface Signal Detect Threshold Reference. he voltage applied to this pin sets the reference level for the fiber interface SD input pin so that the device can directly connect SD pin to both 3.3V and 5V fiber optic tansceivers. Typically, this pin is either tied to GND (for 3.3V) or to an external voltage divider (for 5V). Transmit Current Set. An external resistor connected between this pin and GND will set the level for the transmit outputs.
159
SD_THR
---
140
REXT
---
4
MD400177/B
T T T
84220
1.0 PIN DESCRIPTION (cont'd)
Controller Interface (MII & RMII)
Pin # 87 69 50 31 88 70 51 32 [92:89] [74:71] [55:52] [36:33] 86 68 49 30 Pin Name TXCLK_[3:0] I/O O Description Transmit Clock Output. hese interface outputs provide clocks to external controllers. Transmit data from the controller on TXD, TXEN, and TXER is clocked in on the rising edges of TXCLK and CLKIN. Transmit Enable Input. These interface inputs must be be asserted active high to allow data on TXD and TXER to be clocked in on the rising edges of TXCLK and CLKIN. Transmit Data Input. These interface inputs contain input nibble data to be transmitted on the TP or FX outputs and are clocked in on rising edges of TXCLK and CLKIN. In RMII mode, only TXD[1:0] are used. Transmit Error Input. These interface inputs initiate an error pattern to be transmitted on the TP or FX outputs and are clocked in on rising edges of TXCLK when TXEN is asserted. If the channel is placed in the Bypass 4B5B Encoder mode, these pins are reconfigured to be the fifth TXD transmit data input, TXD4. In RMII mode, these pins are not used. RXCLK_[3:0] O Receive Clock Output. These interface outputs provide a clock to the controller. Receive data on RXD, RXDV, and RXER is clocked out to the controller on falling edges of RXCLK. Carrier Sense Output. hese interface outputs are asserted active high when valid data is detected on the receive TP or FX inputs and is clocked out on the falling edge of RXCLK. Receive Data Valid Output. These interface outputs are asserted active high when valid decoded data is present on the RXD outputs and is clocked out on falling edges of RXCLK. In RMII mode, these pins are not used. Receive Data Output. hese interface outputs contain recovered nibble data from the TP or FX inputs and are clocked out on the falling edges of RXCLK. In RMII mode, only RXD[1:0] are used. Receive Error Output. hese interface outputs are asserted active high when coding or other specified errors are detected on the TP or FX inputs and are clocked out on falling edges of RXCLK. If the channel is placed in the Bypass 4B5B Decoder mode, these pins are reconfigured to be the fifth RXD receive data output, RXD4. COL_[3:0] O Collision Output. These interface outputs are asserted active high when collision between transmit and receive data is detected.
TXEN_[3:0]
I
TXD[3:0]_3 TXD[3:0]_2 TXD[3:0]_1 TXD[3:0]_0 TXER_[3:0]/ TXD4_[3:0]
I
I
84 66 47 28 94 76 58 38 83 65 46 27 [79:82] [61:64] [42:45] [23:26] 85 67 48 29
CRS_[3:0]
O
RXDV_[3:0]
O
RXD[3:0]_3 RXD[3:0]_2 RXD[3:0]_1 RXD[3:0]_0 RXER_[3:0]/ RXD4_[3:0]
O
O
93 75 57 37
5
MD400177/B
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