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Details, datasheet, quote on part number:NQ84221
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| Part: | NQ84221 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) |
| Description: | Quad 10/100 MBPS TX/FX/10BT (PHY) Manual 1/99 |
| Company: | LSI Logic Corporation |
| Datasheet: | Download NQ84221 datasheet File size : 1042 kB |
| Request For quote: | Find where to buy NQ84221
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Datasheet text preview:
s M
84221 84221
Quad 100BaseTX/10BaseT Physical Layer Device
PRELIMINARY
99191
Features
s Single Chip 100BaseTX/10BaseT Physical Layer Solution
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Four Independent Channels in One IC
s 3.3V Power Supply with 5V Tolerant I/O s Dual Speed - 10/100 Mbps s Half and Full Duplex s Reduced Pin Count MII (RMII) Interface to Ethernet Controller s MI Interface for Configuration and Status s Optional Repeater Interface s AutoNegotiation for 10/100, Full/Half Duplex Hardware Controlled Advertisement s Meets all Applicable IEEE 802.3, 10BaseT, 100BaseTX Standards s On Chip Wave Shaping - No External Filters Required s Adaptive Equalizer for 100BaseTX s Baseline Wander Correction s LED Outputs Link Activity Collision Full Duplex 10/100 s128L PQFP
Description
The 84221 is a highly integrated Ethernet Transceiver for twisted pair and fiber Ethernet applications. The 84221 can be configured for either 100BaseTX or 10BaseT Ethernet operation. The 84221 consists of four (4) separate and independent channels. Each channel consists of: 4B5B/Manchester encoder, scrambler, transmitter with wave shaping and onchip filters, transmit output driver, receiver with adaptive equalizer, filters, baseline wander correction, clock and data recovery, descrambler, 4B5B/Manchester decoder, and controller interface (MII or RMII). The addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external filters normally required in 100BaseTX and 10BaseT applications. The 84221 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation, for each channel independently, using the on-chip AutoNegotiation algorithm. The 84221 can access eleven 16-bit registers for each channel through the Management Interface (MI) serial por t. These registers comply to Clause 22 of IEEE 802.3u and contain configuration inputs, status outputs, and device capabilities. The 84221 is ideal as a media interface for 100BaseTX/ 10BaseT switching hubs, repeaters, routers, bridges, and other multi port applications. The 84221 is implemented in a low power CMOS technology and operates with a 3.3V power supply.
1
D400184/A
84221
1.0 Pin Configuration
SPEED_1 128 SPEED_2 107 CRS_DV3 121 SPEED_0 111 REGDEF 117 DPLX_0 104 TXEN_3 116 DPLX_1 105 TXD0_3 103 RXER_3 126 LED3_3 125 LED3_2 114 DPLX_3
106 TXD1_3
124 LED3_1
123 LED3_0
127 CLKIN
115 DPLX_2
120 RESET
110 MDIO
112 MDC
108 GND
119 GND
118 VDD
113 VDD
109 VDD
122
SPEED_3 GND GND TPIP_3 TPIN_3 VDD TPOP_3 GND VDD TPON_3 GND VDD TPON_2 GND VDD TPOP_2 TPIN_2 TPIP_2 REXT GND TPIP_1 TPIN_1 VDD TPOP_1 GND VDD TPON_1 GND VDD TPON_0 GND VDD TPOP_0 TPIN_0 TPIP_0 NC GND LED0_3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 NC 101 RXD0_3 100 RXD1_3 99 98 97 96 95 94 93 92 91 VDD GND CRS_DV2 NC ANEG LEDDEF TXD1_2 TXD0_2 TXEN_2 NC REPEATER RXER_2 NC RXD0_2 RXD1_2 VDD GND CRS_DV1 NC GND PHYAD4 PHYAD3 TXD1_1 TXD0_1 TXEN_1 NC PHYAD2 RXER_1 NC RXD0_1 RXD1_1 CRS_DV0 NC VDD VDD
84221 128 Pin PQFP Top View
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
39
41
40
42
43
44
45
46
47
57
58
59
60
61
62
63 TXD1_0
51
52
53
55
48
49
LED1_2
LED2_3
LED2_2
50
VDD
VDD
AD_REV
LED0_2
LED0_1
LED1_1
LED1_0
LED2_0
GND
GND
54
56
RXER_0
RXD0_0
TXEN_0
LED2_1
LED0_0
LED1_3
TXD0_0
GND
VDD
2
MD400184/A
RXD1_0
GND
NC
64
84221
1.0 PIN DESCRIPTION
Power Supplies
Pin # 6 9 12 15 23 26 29 32 52 53 56 65 66 84 99 109 113 118 2 3 8 11 14 20 25 28 31 37 44 51 55 64 80 83 98 108 119 36 60 67 71 74 81 87 90 96 102 Pin Name VDD I/O -- Description Positive Supply. +3.3 +/-5% Volts.
GND
--
Ground. 0 Volts.
NC
--
No Connect. Reserved for future use, must be left floating for proper operation.
3
MD400184/A
14 5
84221
1.0 PIN DESCRIPTION (cont'd)
Media Interface
Pin # 7 16 24 33 10 13 27 30 18 21 35 TPIN_[3:0] 17 22 34 9 REXT -- Transmit Current Set. An external resistor connected between this pin and GND will set the level for the transmit outputs. I Twisted Pair Receive Input, Negative. Pin Name TPOP_[3:0] I/O O Description Twisted Pair Transmit Output, Positive.
TPON_[3:0]
O
Twisted Pair Transmit Output, Negative.
TPIP_[3:0]
I
Twisted Pair Receive Input, Positive.
4
MD400184/A
TT
84221
1.0 PIN DESCRIPTION (cont'd)
Controller Interface (RMII)
Pin # 127 Pin Name CLKIN I/O I Description Clock Input. This controller interface input latches controller interface data in and out of the device on rising edges for all channels. There must be a 50 Mhz clock tied to this pin. Transmit Enable Input. These interface inputs must be be asserted active high to allow data on TXD and TXER to be clocked in on the rising edges of CLKIN. Transmit Data Input. These interface inputs contain input di-bit data to be transmitted on the TP outputs and are clocked in on rising edges of CLKIN.
104 91 75 61 [106:105] [93:92] [77:76] [63:62] 107 97 82 68 [100:101] [85:86] [69:70] [57:58] 103 88 72 59
TXEN_[3:0]
I
TXD[1:0]_3 TXD[1:0]_2 TXD[1:0]_1 TXD[1:0]_0 CRS_DV[3:0]
I
O
Carrier Sense Output. hese interface outputs are asserted active high when valid data is detected on the receive TP inputs and is clocked out on the rising edge of CLKIN. Receive Data Output. hese interface outputs contain recovered di-bit data from the TP inputs and are clocked out on the rising edges of CLKIN.
RXD[1:0]_3 RXD[1:0]_2 RXD[1:0]_1 RXD[1:0]_0 RXER_[3:0]
O
O
Receive Error Output. hese interface outputs are asserted active high when coding or other specified errors are detected on the TP inputs and are clocked out on rising edges of CLKIN.
5
MD400184/A
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