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Part: QQ80C300
Category:
Communication
-> Network
-> Controllers
Description: 100 Fast Ethernet Controller Manual 1/98
Company: LSI Logic Corporation
Datasheet: Download QQ80C300 datasheet File size : 88 kB
Request For quote: Find where to buy QQ80C300
Datasheet text preview:
Full Duplex
80C80C300 300
HURRICANE
TM
Full Duplex CMOS Ethernet 10/100 Mega Bit/Sec Data Link Controller
98012
Features
s Low Power CMOS Technology s 10/100 MBit Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router, & Server Applications s Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards for Ethernet (10Base-5) Thin Net (10Base-2) (10Base-T) and the Proposed 100Base-T4, 100Base-TX Standards s 10 MHz Serial/Parallel Conversion in 10 MBit/sec Serial Mode. s Standard 10MBit/sec Serial Mode or Programmable MII Ethernet Interface for 10/100 MBit/sec Applications s Programmability of Double Word Threshold Count for Space Available/Data Available Ready Condition for Transmit/Receive FIFOs s Auto Retransmit Upon Collision Sense s Preamble Generation and Removal s Automatic 32-Bit FCS (CRC) Generation and Checking s Collision Handling, Transmission Deferral and Retransmission with Automatic Jam and Backoff Functions s Error Interrupt and Status Generation s Selectable Little Endian/Big Endian Transmit Byte Ordering for FIFO Interface for Intel/Motorola Compatibility s Single 5 Vą 5% Power Supply s Standard CPU and Peripheral Interface Control Signals s 128/128 Byte Independent Transmit/Receive FIFOs with 32 Bit Data Path Interface - 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate in 32 Bit Mode. s Loopback Capability for Diagnostics s 32 Bit FIFO Data Path
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
s Inputs and Outputs TTL Compatible s The Following Additional Features can be Programmed for the 80C300 - 64 bit Multicast Filter - Reports Status of "SQE" During Transmits - Transmit No CRC Mode - Transmit No Preamble Mode - Transmit Packet Autopadding Mode - Receive CRC Mode - Disable Self-Receive on Transmit Mode - Disable Further Transmissions when Both Transmit Status Registers are Full - Disable Loading the Transmit Status for Successfully Transmitted Packets - Disable the Receive Interrupts Independent of the Receive Command Register Setting - Successful Packet Transmit Completion Feature s Full Duplex Operation - Provides 20/200 Mbps Bandwidthfor Switched Networks - Supports AutoDUPLEX Mode for Automatic Full Duplex Operation s Transmit Status on a Per Packet Basis Reports the Following - Occurrence of a Transmit FIFO Underflow - Transmit Collision Occurrence - 16 Collision Occurrence - Carrier Sense Error During Transmission - 10/100 Mbit/sec Transmit Clock Detect - Late Collision Occurrence - Transmission Successful - Transmission Deferred
Hurricane is a trademark of SEEQ Technology Inc.
4-1 1
MD400145/G
80C300
s Management Counters for - Alignment Errors - FCS Errors - Runt Receive Frames - Short Receive Events - Oversized Receive Packets - Transmit Collisions - Receive Collisions - Very Long Transmit Events - Excessive Transmit Deferral - Late Transmit Collisions - Transmit Excessive Collisions
Symbol Errors (100 MBit/sec Ethernet Only) Total Octets Received Total Octets Transmitted Receive FIFO Overflows Total Rx Multicast, Unicast and Broadcast Frames - Total Tx Multicast, Unicast and Broadcast Frames - Tx Defer Count - Number of Retransmit Attempts s 128 Pin PQFP package
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2 4-2
MD400145/G
80C300
Table of Contents 1.0 Pin Description 2.0 Introduction 3.0 Functional Description
3.1 Frame Format 3.2 Packet Transmission 3.2.1 Controlling Transmit Packet Encapsulation 3.2.2 Transmission Initiation/Deferral 3.2.3 Collision on Transmit 3.2.4 Transmit Termination Conditions 3.2.5 Error Conditions That Will Cause TXRET to go HIGH 3.2.6 Detection and Clearing of a Transmit Retry Condition 3.3 Packet Reception 3.3.1 Preamble Processing 3.3.2 Address Matching 3.3.3 Conditions of Receive Termination 3.3.4 Using Rxabort to Terminate Reception 3.3.5 Receive Discard Conditions 3.4 System Interface 3.5 FIFO Interface 3.5.1 Little and Big Endian Format 3.5.2 Transmit FIFO Interface 3.5.3 Receive FIFO Interface 3.5.4 Special Conditions on RXRD_TXWR Clock Input 3.6 Register Interface 3.6.1 Internal Channel Register Addressing Table 3.6.2 Station Address Register 3.6.3 Transmit Command Register Receive Command Register Transmit Status Register Receive Status Register Configuration Registers FIFO Threshold Register 3.6.8.1 FIFO Threshold Register Address Settings Table 3.6.9 Defer Register Calculations for 80C300 3.7 Management Interface of the MII 3.8 Counters 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8
4.0 DC Characteristics 5.0 AC Characteristics
5.01 Command/Status Interface Read Timing 5.02 Command/Status Interface Write Timing
6.0 Ethernet Transmit and Receive Interface Timing
6.01 Ethernet Transmit Interface Timing 6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Timing
7.01 Transmit Data Interface Write Timing 1 7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Timing
8.01 Receive Data Interface Read Timing 1 8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on Exception Conditions 10.0 Receive Data Interface Timing on Exception Conditions 11.0 Reset Timing
Illustrations
Figure 1. Functional Block Diagram of the 80C300 Figure 2. 80C300 Pin Configuration Figure 3. Typical Application Example
4-3 3
MD400145/G
TRANSMIT BYTE COUNTER BUSSIZE BE1 ATTEMPT COUNTER BACKOFF CONTROLLER BE0 A [5:0] ENREGIO RD WR CDST [15:0]
MD400145/G
TRANSMIT BYTE CONTROL CSN REGISTER INTERFACE & TRI-STATE LOGIC RXNOCRC CONTROL REGISTER FILE INTERRUPT AND CONTROL INT CRC/DATA SELECT MODE 100 M U X 128 BYTE TRANSMIT FIFO PARALLEL /SERIAL CRC GENERATOR M U X TXDO M U X TXD [3:1] DOUBLE WORD TO NIBBLE TRI-STATE CONTROL & FIFO INTERFACE LOGIC CRC CHECKER RXD0 RXD [3:1] CRC STRIPPER TRI-STATECONT ROL LOGIC CSN FRAMING AND ERROR CONTROL RX_DV BIT/NIBBLE TO BYTE CONVERTER RXINTEN RXABORT ADDRESS CHECKER RXDC RXC RECEIVE COUNTER CLOCK DRIVERS TXC SPACE LOGIC BYTE TO DOUBLE WORD PACKER RECEIVE BYTE CONTROL 128 BYTE RECEIVE FIFO RXBYT12 RXOVF
T16COLL
TXNOCRC
COLL
TXRET
TXEN
CLRTXERR
TXWREN
RXRDEN
RXINTEN
TXINTEN
TXRDY
4 4-4
BUSMODE
RXTXDATA [31:0]
RXTXBE [3:0]
RXTXEOF
RXRD_TXWR
SPDTAVL
RXRDY
80C300
Figure 1. 80C300 Functional Block Diagram
80C300
RXTXDATA0 RXTXDATA1 DAISY_OUT ADUPLX RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 TXEN MDI O COLL TXD0 TXD1 TXD2 TXD3
MDC
GND
GND
GND
GND 104
112
111
110
109
RXC
TXC
108
107
106
105
122
121
120
119
118
117
116
115
114
128
127
126
125
124
123
113
103
GND
CSN
VDD GND WR RD BE0 BE1 A5 A4 A3 A2 A1 A0 CDST15 CDST14 CDST13 CDST12 CDST11 GND VDD CDST10 CDST9 CDST8 CDST7 CDST6 CDST5 GND CDST4 CDST3 CDST2 CDST1 CDST0 ENREGI0 BUSSIZE BUSMODE RXTXBE3 RXTXBE2 VDD GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88
VDD GND RXTXDATA2 RXTXDATA3 RXTXDATA4 RXTXDATA5 RXTXDATA6 RXTXDATA7 RXTXDATA8 RXTXDATA9 RXTXDATA10 RXTXDATA11 GND RXTXDATA12 RXTXDATA13 RXTXDATA14 RXTXDATA15 RXTXDATA16 VDD RXTXDATA17 RXTXDATA18 RXTXDATA19 RXTXDATA20 RXTXDATA21 GND RXTXDATA22 RXTXDATA23 RXTXDATA24 RXTXDATA25 RXTXDATA26 GND RXTXDATA27 RXTXDATA28 RXTXDATA29 RXTXDATA30 RXTXDATA31 GND GND
80C300 128 PQFP
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63 GND
TXWREN
TXNOCRC
RXBYT12
VDD
INT
CLRTXERR
RXABORT
SPDTAVL
RXTXEOF
RXTXBE0
RXRDEN
RXRDY
RXOVF
TXRDY
RXDC
VDD
TXINTEN
TXRET
RXRD_TXWR
Figure 2. 80C300 Pin Configuration
CLRRXERR
RXTXBE1
RXINTEN
4-5 5
MD400145/G
T16COLL
RESET
VDD
64
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