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Details, datasheet, quote on part number:QQ84301
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| Part: | QQ84301 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) |
| Description: | 4-Port Fast Ethernet Controller Manual 3/98 |
| Company: | LSI Logic Corporation |
| Datasheet: | Download QQ84301 datasheet File size : 621 kB |
| Request For quote: | Find where to buy QQ84301
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Datasheet text preview:
Full Duplex
84301 4-Port FastURRICANE Ethernet Controller H 4-Port
TM
84301
98079
Fast Ethernet Controller
This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access SEEQ Home Page www.seeq.com - or LSI Logic at www.lsilogic.com - Disable Loading the Transmit Status for Successfully Transmitted Packets - Disable the Receive Interrupts Independent of the Receive Command Register Setting
s Fifteen 32-bit Counters per Port for Network Management Statistics Receive: - CRC Errors - Runt Frames - Oversize Frames - Alignment Errors - Collisions - FIFO Underflow Transmit: - Single Retry Collisions - Multiple Retry Collisions - Sixteen Retry Collisions - FIFO Underruns - Late Collisions - Loss of Carrier - Transmit Deferred - Total Frames - Total Octets s Full Duplex Operation - Provides 20/200 Mbps Bandwidth for Switched Networks - Supports AutoDUPLEX Mode for Automatic Full Duplex Operation s High Bandwidth Bus Interface - 32 Bits x 33 MHz - Selectable Big/Little Endianess s Independent 128 Byte Transmit/Receive FIFOs/Port - Programmable Threshold Flags s Full Backward Compatibility with 84C300A s Error Interrupts and Status Conditions Examples: - Counter Half-Full - Rx FIFO Overflow - Tx FIFO Underflow s 208 Pin PQFP package
Features
s Low Power CMOS Technology s 4-Port Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router, Server Applications s Supports 100Base-T4, 100 Base-TX, 100Base-FX & 10Base-T Transceivers s Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards for Thicknet (10Base-5), Thin Net (10Base-2) and Twisted Pair (10Base-T) s Standard 10MBit/sec Serial Mode or Programmable MII Ethernet Interface for 10/100 MBit/sec Applications s Preamble Generation and Removal s Automatic 32-Bit FCS (CRC) Generation and Checking s Collision Handling, Transmission Deferral and Retransmission with Automatic Jam and Backoff Functions s Transmit Status on a Per Packet Basis Reports the Following - Occurrence of a Transmit FIFO Underflow - Transmit Collision Occurrence - 16 Collision Occurrence - Carrier Sense Error During Transmission - 10/100 Mbit/sec Transmit Clock Detect - Late Collision Occurrence - Transmission Successful - Transmission Deferred s Single 5 Vą 5% Power Supply s Loopback Capability for Diagnostics s The Following Additional Features can be Programmed for the 84301 - 64 bit Multicast Filter - Reports Status of "SQE" During Transmits - Transmit No CRC Mode - Transmit No Preamble Mode - Transmit Packet Autopadding Mode - Receive CRC Mode - Disable Self-Receive on Transmits Mode - Disable Further Transmissions when Both Transmit Status Registers are Full
Hurricane is a trademark of SEEQ Technology Inc.
4-1 1
MD400158/D
84301 4-Port Fast Ethernet Controller Table of Contents 1.0 Pin Description 2.0 Introduction 3.0 Functional Description
3.1 Frame Format 3.2 Packet Transmission per Port 3.2.1 Controlling Transmit Packet Encapsulation 3.2.2 Transmission Initiation/Deferral 3.2.3 Collision on Transmit 3.2.4 Transmit Termination Conditions 3.2.5 Conditions That Will Cause a Port's TXRET Pin to go HIGH 3.2.6 Detecting and Clearing a Transmit Retry Condition 3.3. Packet Reception Per Port 3.3.1 Preamble Processing 3.3.2 Address Matching 3.3.3 Terminating Reception 3.3.4 Using the RXABORT Pins to Terminate Reception of a Packet 3.3.5 Receive Discard Conditions 3.4 System Interface 3.5 FIFO Interface 3.5.1 Little Endian and Big Endian Format 3.5.2 Transmit FIFO Interface 3.5.3 Receive FIFO Interface 3.5.4 Special Conditions on RXRD_TXWR Clock Input 3.6 Register Interface 3.6.1 Internal Port Register Addressing Table 3.6.2 Station Address Register 3.6.3 Transmit Command Register 3.6.4 Transmit Status Register 3.6.5 Receive Command Register Receive Status Register Configuration Registers FIFO Threshold Register Defer Register Calculations for the 84301 3.6.10 Transmit Control/Product I.D. Register 3.6.11 Full Duplex Status Register 3.7 Counters 3.7.1 Accessing the Counters 3.7.2 Counter Value after Read Operation Completion 3.7.3 Counter Behavior Upon Reading Maximum Count 3.7.4 Counter Interrupt Condition 3.6.6 3.6.7 3.6.8 3.6.9
4.0 DC Characteristics 5.0 Command/Status Interface Timing
5.01 Command/Status Interface Read Timing 5.02 Command/Status Interface Write Timing
6.0 Transmit Interface Timing
6.01 Ethernet Transmit Interface Timing 6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Write Timing
7.01 Transmit Data Interface Write Timing 1 7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Read Timing
8.01 Receive Data Interface Read Timing 1 8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on Exception Conditions 10.0 Receive Data Interface Timing on Exception Conditions 11.0 Reset Timing
Illustrations
Figure 1. Functional Block Diagram of the 84301 Figure 2. 84301 Pin Configuration Figure 3. Typical Application Example
2 4-2
MD400158/D
84301 4-Port Fast Ethernet Controller 1.0 Pin Description
Pin Pin Name I/O Description Chip Registers' Interface 22 ENREGIO I Enable Register I/O Operations This active low input enables the chip for register operations. This input must be low before any port's registers can be written or read. Write Strobe For a selected port within the chip, this input acts as a write strobe for one of the port's registers. The port is selected through the REGPS[1:0] inputs and the register is addressed through the A[4:0] address inputs. The data being written appears on the CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe. This input is active low. Read Strobe For a selected port within the chip, this input acts as a read strobe for one of the port's registers. The port is selected through the REGPS[1:0] inputs and the register is addressed through the A[4:0] address inputs. When the read strobe is active low, the output drivers for CDST[7:0] data bus are enabled. Valid register data appears on the data bus a specified time before the rising edge of the read strobe. Register Port Select Inputs These inputs are used to select which port's registers are read or written by asserting the RD or WR read or write strobe inputs. Binary values of 00 through 11 select channels 1 through 4 respectively with REGPS1 being the MSB of the binary value. REGPS1 REGPS0 0 0 1 1 206, 153, 6, 7, 8 A[4:0] I 0 1 0 1 Selected Port Port 1 Port 2 Port 3 Port 4
4
WR
I
5
RD
I
21, 20
REGPS[1:0]
I
Register Select Address These inputs are the address lines used to select which register within a port is being read or written. A3 (153) and A4 (206) each has an internal pull down to ensure backward compatibility with the 84C300A. Register Data These bidirectional lines carry register data to or from the internal registers of each port in the chip. These lines are nominally high impedance until their output drivers are enabled by the RD and ENREGIO input pins being driven low. Interrupts These outputs are driven by a variety of Transmit and Receive interrupt conditions of a particular port. If remains HIGH until the corresponding port's Status Register containing the reason for the interrupt is read. Hardware Reset This input is an active low asynchronous chip reset. After reset, all registers except the Hash and Station Address registers are reset to zero, all FIFOs are cleared, all counters are reset to zero.
9-12 15-18
CDST[7:0]
I/O
47, 61, 68, 77
INT_[1:4]
O
49
RESET
I
4-3 3
MD400158/D
84301 4-Port Fast Ethernet Controller Pin Description (cont.)
Pin Pin Name I/O Description Receive and Transmit FIFO Interface 31 RXINTEN I Receive Interface Enable This is an active low input that acts as a chip enable to enable the receiver interface. Driving this pin active enables the output drivers for the RXDC[1:4] and RXRDY[1:4], pins. Also, this pin must be driven active before receive FIFO reads can be performed. Transmit Interface Enable This is an active low input that acts as a chip enable to enable the transmitter interface. Driving this pin active enables the output drivers for the TXRET[1:4], TXRDY[1:4] pins. Also, this pin must be driven active before transmit FIFO writes can be and performed. Receive Read Enable This is an active low input that, when driven active with the RXINTEN pin, enables read operations from one of the four receive FIFOs within the chip. Transmit Write Enable This is an active low input that, when driven active with the TXINTEN pin, enables write operations to one of the four transmit FIFOs within the chip. Receive Read Transmit Write Clock This clock input is also the chip's read/write strobe to the chip's eight receive/transmit FIFOs. With the TXINTEN and TXWREN inputs active low, this input becomes the write strobe for writing transmit data to one of the chip's transmit FIFOs. Similarly, with the RXINTEN and RXRDEN inputs active low, this input becomes the read strobe for reading receive data from one of the chip's receive FIFOs. This input must be connected to a continuous clock whose maximum frequency can be 33 MHz. Port Select These inputs are used to select and identify which port will be accessed for the following operations. 1. Receive FIFO Reads 2. Transmit FIFO Writes 3. Clearing a TXRET Condition 4. Clearing a RXDC Condition 5. Aborting a Receive Packet RXTXPS[1:0] RXTXPS1 0 0 1 1 23, 24 25, 26 RXTXBE[3:0] I/O RXTXPS0 0 1 0 1 Selected Port Port 1 Port 2 Port 3 Port 4
32
TXINTEN
I
36
RXRDEN
I
37
TXWREN
I
35
RXRD_TXWR
I
30, 29
RXTXPS[1:0]
I
Receive Transmit Byte Enable These are active low bidirectional signals that determine which bytes of the double word for a receive FIFO read are driven with valid data or which bytes of a double word being written to a transmit FIFO contain valid data.
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MD400158/D
84301 4-Port Fast Ethernet Controller Pin Description (cont.)
Pin 44, 57 64, 73 Pin Name TXRDY_ [1:4] I/O O Description Transmit Ready These are active high three state outputs. When enabled, these outputs function as a flag that indicates whether the associated port's transmit FIFO has enough space available to meet the threshold value programmed in the FIFO threshold register. When enabled, a high value on any of these outputs indicates that the associated port's transmit FIFO has greater than or equal to the threshold number of double word spaces available in the FIFO and a low value indicates it does not. The tristate drivers for all these outputs are enabled by a low value on the TXINTEN input pin. Receive Ready These are active high three state outputs. When enabled, these outputs function as a flag that indicates whether the associated port's receive FIFO has enough data available to meet the threshold value programmed in the FIFO threshold register. When enabled, a high value on any of these outputs indicates that the associated port's receive FIFO has greater than or equal to the threshold number of double words available in the FIFO or has a completed receive packet in the FIFO as indicated by the packets status double word being in the FIFO. The tristate drivers for all these outputs are enabled by a low value on the RXINTEN input pin. Space Data Available This is an active high output that can be used for validating reads from the receive FIFO during a read operation and preventing over writes to the transmit FIFO during a write operation. For further details, please refer to the Transmit Data Write Timing and the Receive Data Read Timing diagrams. Receive Transmit End of Frame This is a bidirectional pin that is used to signal the last double word of a transmit or receive packet. During receive FIFO reads this pin is enabled as an output and when detected high indicates that the last double word of a receive packet has been read from the receive FIFO. During transmit FIFO writes this pin is an input and when asserted high during a write it indicates that this is the final double word of a transmit packet. In the transmit FIFO write case the value of this signal is stored as the 33rd bit in the FIFO. In the receive FIFO read case the value of this signal is read out as the 33rd bit of the receive FIFO. Transmit No CRC This active high input is used to control appending of a CRC to a transmit packet. A transmit packet can be made to exclude appending a CRC value if this input is held high any time during a packet write to the transmit FIFO. Transmission of all packets without CRC can be done by setting bit #4 of configuration register #1. It should be noted that TXNOCRC pin can be used to control CRC encapsulation only on a per packet basis. Receive/Transmit Data This is the bidirectional data bus for reads from the receive FIFO or writes to the transmit FIFO of the chip. Bus direction is controlled via RXINTEN and RXDEN for reads; TXINTEN and TXWREN are used for writes. Data is clocked with the RXRD_TXWR strobe input.
42, 56 63, 72
RXRDY_ [1:4]
O
39
SPDTAVL
O
40
RXTXEOF
I/O
41
TXNOCRC
I
80-84 86-89 91-94 96-101 107-112 115-121
RXTXDATA[31:0]
I/O
4-5 5
MD400158/D
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