|
Details, datasheet, quote on part number:QQ84C30A
| |
Datasheet text preview:
Full Duplex
4-Port 84C30A
84C30A
96339
4-Port Ethernet Controller
Features
s Low Power CMOS Technology s 4-Port Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router, Server Applications s Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards for Thicknet (10Base-5), Thin Net (10Base-2) and Twisted Pair (10Base-T) s Standard 10MBit/sec Serial Ethernet s Selectable Little Endian/Big Endian Transmit Byte Ordering for FIFO Interface for Intel/Motorola Compatibility s Open Bus Interface s Programmability of Double Word Threshold Count for Space Available/Data Available Ready Condition for Transmit/Receive FIFO's s Auto Retransmit Upon Collision Sense s Preamble Generation and Removal s Automatic 32-Bit FCS (CRC) Generation and Checking s Collision Handling, Transmission Deferral and Retransmission with Automatic Jam and Backoff Functions s Error Interrupt and Status Generation s Single 5 Vą 5% Power Supply s Standard CPU and Peripheral Interface Control Signals s Independent 128 Byte Transmit/Receive FIFOs on each Port - 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate in 32 Bit Mode. s Loopback Capability for Diagnostics s 32 Bit FIFO Data Path s Inputs and Outputs TTL Compatible s The Following Additional Features can be Programmed for the 84C30A - 64 bit Multicast Filter - Reports Status of "SQE" During Transmits - Transmit No CRC Mode
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
-
Transmit No Preamble Mode Transmit Packet Autopadding Mode Receive CRC Mode Disable Self-Receive on Transmits Mode Disable Further Transmissions when Both Transmit Status Registers are Full - Disable Loading the Transmit Status for Successfully Transmitted Packets - Disable the Receive Interrupts Independent of the Receive Command Register Setting
s Transmit Status on a Per Packet Basis Reports the Following - Occurrence of a Transmit FIFO Underflow - Transmit Collision Occurrence - 16 Collision Occurrence - Carrier Sense Error During Transmission - 10 Mbit/sec Transmit Clock Detect - Late Collision Occurrence - Transmission Successful - Transmission Deferred s Each Port Includes the Following Counters or Status Bits for Network Management Statistics - 16 Bit Short Receive Frame Counter - 16 Bit Alignment Error Counter - 16 Bit CRC Error Counter - 8 Bit Oversize Receive Frame Counter - 16 Bit Transmit Collision Counter - 16 Bit Total Collision Counter - Transmit Status Bits for "Carrier" and "SQE" During Transmits s Full Duplex Operation - Provides 20 Mbps Bandwidth for Switched Networks - Supports AutoDUPLEX Mode for Automatic Full Duplex Operation s 208 Pin PQFP package
4-1 1
MD400151/C
4-Port 84C30A Table of Contents 1.0 Pin Description 2.0 Introduction 3.0 Functional Description
3.1 Frame Format 3.2 Packet Transmission per Port 3.2.1 Controlling Transmit Packet Encapsulation 3.2.2 Transmission Initiation/Deferral 3.2.3 Collision on Transmit 3.2.4 Transmit Termination Conditions 3.2.5 Conditions That Will Cause a Port TXRET Pin to go HIGH 3.2.6 Detecting and Clearing of a Transmit Retry Condition 3.3. Packet Reception Per Port 3.3.1 Preamble Processing 3.3.2 Address Matching 3.3.3 Terminating Reception 3.3.4 Using the Rxabort Pins to Terminate Reception of a Packet 3.3.5 Receive Discard Conditions 3.4 System Interface 3.5 FIFO Interface 3.5.1 Little and Big Endian Format 3.5.2 Transmit FIFO Interface 3.5.3 Receive FIFO Interface 3.5.4 Special Conditions on RXRD_TXWR Clock Input 3.6 Register Interface 3.6.1 Internal Channel Register Addressing Table 3.6.2 Station Address Register 3.6.3 Transmit Command Register 3.6.4 Transmit Status Register 3.6.5 Receive Command Register 3.6.6 Receive Status Register 3.6.7 Configuration Registers 3.6.8 FIFO Threshold Register 3.6.8.1 FIFO Threshold Register Address Settings Table 3.6.9 Defer Register Calculations for the 84C30A 3.6.10 Transmit Control/Product I.D. Register 3.7 Counters
4.0 DC Characteristics 5.0 AC Characteristics
5.01 Command/Status Interface Read Timing 5.02 Command/Status Interface Write Timing
6.0 Ethernet Transmit and Receive Interface Timing
6.01 Ethernet Transmit Interface Timing 6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Timing
7.01 Transmit Data Interface Write Timing 1 7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Timing
8.01 Receive Data Interface Read Timing 1 8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on Exception Conditions 10.0 Receive Data Interface Timing on Exception Conditions
Illustrations
Figure 1. Functional Block Diagram of the 84C30A Figure 2. 84C30A Pin Configuration Figure 3. Typical Application Example
2 4-2
MD400151/C
4-Port 84C30A 1.0 Pin Description
Pin Pin Name I/O Description Chip Registers' Interface 22 4 ENREGIO WR I I This active low input enables the chip for register operations. This input must be low before any port's registers can be written or read. For a selected port within the chip, this input acts as a write strobe for one of the port's registers. The port is selected through the REGPS[1:0] inputs and the register is addressed through the A[2:0] address inputs. The data being written appears on the CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe. This input is active low. For a selected port within the chip, this input acts as a read strobe for one of the port's registers. The port is selected through the REGPS[1:0] inputs and the register is addressed through the A[2:0] address inputs. When the read strobe is active low, the output drivers for CDST[7:0] data bus are enabled. Valid register data appears on the data bus a specified time before the rising edge of the read strobe. These inputs are used to select which port's registers are read or written by asserting the RD or WR read or write strobe inputs. Binary values of 00 through 11 select channels 1 through 4 respectively with REGPS1 being the MSB of the binary value. These inputs are the address lines used to select which register within a port is being read or written. A3 has an internal pull down. These bidirectional lines carry register data to or from the internal registers of each port in the chip. These lines are nominally high impedance until their output drivers are enabled by the RD and ENREGIO input pins being driven low. This output is driven high by a variety of port #1 transmit and receive interrupt conditions. It remains high until the port #1 status register containing the reason for the interrupt is read. This output is driven high by a variety of port #2 transmit and receive interrupt conditions. It remains high until the port #2 status register containing the reason for the interrupt is read. This output is driven high by a variety of port #3 transmit and receive interrupt conditions. It remains high until the port #3 status register containing the reason for the interrupt is read. This output is driven high by a variety of port #4 transmit and receive interrupt conditions. It remains high until the port #4 status register containing the reason for the interrupt is read. This input is an active low chip reset. During reset all registers are reset to zero, all FIFO's are cleared, all counters are reset to zero, and all the inputs to the output drivers for the RXDC and TXRET outputs are driven high.
5
RD
I
21, 20
REGPS[1:0]
I
153, 6, 7, 8 5-8 9-12 7
A[3:0] CDST[7:0]
I I/O
INT_1
O
61
INT_2
O
68
INT_3
O
77
INT_4
O
49
RESET
I
Receive and Transmit FIFO Interface 31 RXINTEN I This is an active low input that acts as a chip enable to enable the receiver interface. Driving this pin active enables the output drivers for the RXDC_1, RXDC_2, RXDC_3, RXDC_4, RXRDY_1, RXRDY_2, RXRDY_3, and RXRDY_4 pins. Also, this pin must be driven active before receive FIFO reads can be performed. This is an active low input that acts as a chip enable to enable the transmitter interface. Driving this pin active enables the output drivers for the TXRET_1, TXRET_2, TXRET_3, TXRET_4, TXRDY_1, TXRDY_2, TXRDY_3, and TXRDY_4 pins. Also, this pin must be driven active before transmit FIFO writes can be performed.
32
TXINTEN
I
4-3 3
MD400151/C
|
|
