Details, datasheet, quote on part number: 27C512-10
Part27C512-10
Category
Description512k-bit [64kx8] CMOS Eprom
CompanyMacronix America, Inc.
DatasheetDownload 27C512-10 datasheet
Quote
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Features, Applications
FEATURES

x 8 organization Single +5V power supply +12.5V programming voltage Fast access time: 45/55/70/90/100/120/150ns Totally static operation Completely TTL compatible

Operating current: 30mA Standby current: 100uA Package type:

The a 5V only, 512K-bit, One-Time Programmable Read Only Memory. It is organized as 64K words by 8 bits per word, operates from a single +5volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM programmers may be used. The MX27C512 supports intelligent fast programming algorithm which can result in programming time of less than fifteen seconds. This EPROM is packaged in industry standard 28 pin dual-in-line packages 32 lead PLCC, and 28 lead TSOP(I) packages.


SYMBOL Q0~Q7 CE OE/VPP NC VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input/Program Supply Voltage No Internal Connection Power Supply Pin (+5V) Ground Pin

THE PROGRAMMING OF THE MX27C512 When the MX27C512 is delivered, it is erased, the chip has all 512K bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C512 through the procedure of programming. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. When programming an MXIC EPROM, a 0.1uF capacitor is required across Vpp and ground to suppress spurious voltage transients which may damage the device. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 5 C ambient temperature range that is required when programming the MX27C512. To activate this mode, the programming equipment must force 0.5(VH) on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte A0 = VIL) represents the manufacturer code, and byte (A0 = VIH), the device identifier code. For the MX27C512, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit.

FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage OE/VPP 12.75V is applied, with VCC 6.25 V, (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC 10%.

READ MODE The MX27C512 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.

PROGRAM INHIBIT MODE Programming of multiple MX27C512s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C512 may be common. A TTL low-level program pulse applied MX27C512 CE input with OE/VPP 0.5V will program that MX27C512. A high-level CE input inhibits the other MX27C512s from being programmed.

STANDBY MODE The MX27C512 has a CMOS standby mode which reduces the maximum VCC current It is placed in CMOS standby when is at VCC 0.3 V. The MX27C512 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.

PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE/VPP and CE, at VIL. Data should be verified tDV after the falling edge of CE.

TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIH VCC0.3V VIL VIH VIL OE/VPP VIL VIH X VPP VIL VPP VIL A0 VIL VIH A9 VH OUTPUTS DOUT High Z High Z High Z DIN DOUT High C2H 91H

A15 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming.


 

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