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Details, datasheet, quote on part number:MX26C1000BMC-15
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| Part: | MX26C1000BMC-15 |
| Category: | Memory => ROM => MTP ROM => 5 Volt Single Power /Fast Programming Operation |
| Description: | Access Time: 150; 1-Mbit (128K X 8) CMOS Multiple-time-programmable-ePROM |
| Company: | Macronix America, Inc. |
| Datasheet: | Download MX26C1000BMC-15 datasheet File size : 1040 kB |
| Request For quote: | Find where to buy MX26C1000BMC-15
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Datasheet text preview:
A D V A N C E INFORMATION
MX26C1000B
FEATURES
1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM · · · · ·
50 minimum erase/program cycles Chip erase time: 1 (typ.) Chip program time: 6.25 (typ.) Typical fast programming cycle duration 10us/byte Package type: - 32 pin plastic DIP - 32 pin PLCC - 32 pin TSOP - 32 pin SOP
· 128Kx 8 organization · Single +5V power supply · +12V programming voltage · Fast access time:90/100/120/150 ns · Totally static operation · Completely TTL compatible · Operating current:30mA · Standby current: 100uA
GENERAL DESCRIPTION
The MX26C1000B is a 5V only, 1M-bit, MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 128K words by 8 bits per word, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. It is design to be programmed and erased by an
EPROM programmer or on-board. The MX26C1000B supports a intelligent fast programming algorithm which can result in programming time of less than one minute. This MTP EPROMTM is packaged in industry standard 32 pin dual-in-line packages, 32 lead PLCC, 32 lead SOP and 32 lead TSOP packages.
PIN CONFIGURATIONS
VCC VPP A12 A15 A16 WE
Q1
Q2
GND
Q3
Q4
Q5
32 TSOP
PIN DESCRIPTION
A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
SYMBOL A0~A16 Q0~Q7 CE OE WE VPP NC VCC GND
PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Program Supply Voltage No Internal Connection Power Supply Pin (+5V) Ground Pin
REV. 0.7, NOV. 20, 2002
MX26C1000B
P/N: PM0767
1
Q6
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
30 29
NC
32 PDIP/SOP
32 PLCC
A14 A13 A8 A9
MX26C1000B
9
MX26C1000B
25
A11 OE A10 CE
13 14
17
21 20
Q7
MX26C1000B
BLOCK DIAGRAM
WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE PROGRAM/ERASE STATE MACHINE (WSM)
X-DECODER
MX26C1000B FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A16 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
P/N: PM0767
2
REV. 0.7, NOV. 20, 2002
MX26C1000B
FUNCTIONAL DESCRIPTION
The set-up Program command (40H) is the only command that requires a two sequence reset cycle. The first Reset command is interpreted as program data. How ever, FFH data is considered null data during programming operations (memory cells are only programmed from logica "1" to "0". The second Reset command safely aborts the programming operation and resets the device to the Read mode. This detailed information is for your reference. It may prove esier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the set-up Program state or not.
When the MX26C1000B is delivered, or it is erased, the chip has all 1000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C1000B through the procedure of programming.
ERASE ALGORITHM
The MX26C1000B do not required preprogramming before an erase operation. The erase algorithm is a close loop flow to simultaneously erase all bits in the entire array. Erase operation starts with the initial erase operation. Erase verification begins at address 0000H by reading data FFH from each byte. If any byte fails to erase. the entire chip is reerased. to a maximum for 30 pulse counts of 100ms duration for each pulse. The maximum cumulative erase time is 3s. However. the device is usually erased in no more than 3 pulses. Erase verification time can be reduced by storing the address of the last byte that failed. Following the next erase operation verification may start at the stored address location. JEDEC standard erase algorithm can also be used. But erase time will increase by performing the unnecessary preprogramming.
SET-UP PROGRAM/PROGRAM
A three-step sequence of commands is required to perform a complete program operation: Set Up ProgramProgram-Program Verify. The device is bulk erased and byte by byte programming. The command 40H is written to the command register to initiate Set Up Program operation. Address and data to be programmed into the byte are provided on the second WE pulse. Addresses are latched on the falling edge of the WE pulse, data are latched on the rising edge of the WE pulse. Program operation begins on the rising edge of the second WE pulse, and terminate of the next rising edge of the WE pulse. Refer to AC Characteristics and Waveforms for specific timing parameters.
PROGRAM ALGORITHM
The device is programmed byte by byte. A maximum of 25 pulses. each of 10us duration is allowed for each byte being programmed. The byte may be programmed sequentially or by random. After each program pulse, a program verify is done to determine if the byte has been successfully programmed. Programming then proceeds to the next desired byte location. JEDEC standard program algorithms can be used.
COMMAND REGISTER
When high voltage is applied to VPP the command register is enabled. Read, write, standby, output disable modes are available. The read, erase, erase verify, program, program verify and Device ID are accessed via the command register. Standard microprocessor write timings are used to input a command to the register. This register serves as the input to an internal state machine which controls the operation mode of the device. An internal latch is used for write cycles, addresses and data for programming and erase operations.
RESET
The Reset command initializes the MTP EPROMTM device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the set-up Program command (40H). This will safely abort any previous operation and initialize the device to the Read mode.
NO INTEGRATED STOP TIMER FOR ERASE
Leading industry flash technology requires a stop timer built into the flash chip to prevent the memory cells from going into depletion due to over erase. The 1 Mbit MTP
P/N: PM0767
3
REV. 0.7, NOV. 20, 2002
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