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Details, datasheet, quote on part number:MX26L6420XBI-90
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Datasheet text preview:
MX26L6420
64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
· 4,194,304 x 16 byte structure · Single Power Supply Operation - 3.0 to 3.6 volt for read, erase and program operations · Low VCC write inhibit is equal to or less than 2.5V · Compatible with JEDEC standard · High Performance - Fast access time: 90/100/120ns (typ.) - Fast program time: 140s/chip (typ.) - Fast erase time: 150s/chip (typ.) · Low Power Consumption - Low active read current: 17mA (typ.) at 5MHz - Low standby current: 30uA (typ.) · Provides a 512 word area for code or data that can be permanently protected. Once this sector is protected, it is prohibited to program or erase within the sector again. · Minimum 100 erase/program cycle · Status Reply - Data polling & Toggle bits provide detection of program and erase operation completion · 12V ACC input pin provides accelerated program capability · Output voltages and input voltages on the device is deter mined by the voltage on the VI/O pin. - VI/O voltage range:1.65V~3.6V · 10 years data retention · Package - 44-Pin SOP - 48-Pin TSOP
GENERAL DESCRIPTION
The MX26L6420 is a 64M bit MTP EPROMTM organized as 4M bytes of 16 bits. MXIC's MTP EPROMTM offer the most cost-effective and reliable read/write non-volatile random access memory. The MX26L6420 is packaged in 44-pin SOP and 48-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX26L6420 offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26L6420 has separate chip enable (CE) and output enable OE controls. MXIC's MTP EPROMTM augment EPROM functionality with in-circuit electrical erasure and programming. The MX26L6420 uses a command register to manage this functionality. MXIC's MTP EPROMTM technology reliably stores memory contents even after 100 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX26L6420 uses a 3.0V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.
P/N:PM0823
REV. 1.1, JUL. 16, 2003
1
MX26L6420
PIN CONFIGURATION 44 SOP
A21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 WE GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
48 TSOP
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE RESET ACC VCC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VI/O GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
MX26L6420
MX26L6420
PIN DESCRIPTION
SYMBOL A0~A21 Q0~Q15 CE WE OE RESET VCC ACC VI/O GND PIN NAME Address Input Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low (for 48 TSOP only) Power supply Hardware Acceleration Pin (for 48 TSOP only) I/O power supply (for 48 TSOP only) Device Ground
LOGIC SYMBOL
21 A0-A21 Q0-Q15 16
CE OE WE RESET ACC
P/N:PM0823
REV. 1.1, JUL. 16, 2003
2
MX26L6420
BLOCK DIAGRAM
WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX26L6420 FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A21 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q15
I/O BUFFER
P/N:PM0823
REV. 1.1, JUL. 16, 2003
3
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