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Details, datasheet, quote on part number:MX27C4111-10
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Datasheet text preview:
PRELIMINARY
MX27C4111
4M-BIT [512K x8/256K x16] CMOS EPROM WITH PAGE MODE
FEATURES
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With Page Mode function, 8-word/16-byte page 512K x 8 or 256K x 16 organization +12.5V programming voltage Fast access time: 90/100/120/150 ns Page mode access time 50/60/75 ns Totally static operation
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Completely TTL compatible Operating current: 60mA Standby current: 100uA Package type: - 40 pin plastic DIP - 40 pin SOP
GENERAL DESCRIPTION
The MX27C4111 is a 4M-bit, One Time Programmable Read Only Memory with page mode. It is organized as 512K x 8 or 256K x 16, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM programmers may be used. The MX27C4111 supports a intelligent fast programming algorithm which can result in programming time of less than two minutes. MX27C4111 provides Page Read Access Mode which can greatly reduce the read access time. Normal read access time and Page Mode read access time is as fast as 90/50ns. It is designed to be compatible with all microprocessors and similar applications in which high perofmrance, large bit storage and simple interfacing are important design considerations. This EPROM is packaged in industry standard 40 pin dual-in-line packages and 40 pin SOP packages.
PIN CONFIGURATIONS PDIP/SOP
A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
BLOCK DIAGRAM
CE OE BYTE/VPP CONTROL LOGIC OUTPUT BUFFERS Q0~Q14 Q15/A-1
MX27C4111
. . A0~A17 ADDRESS INPUTS . . . . . .
Y-DECODER
. . . . . . . .
Y-SELECT
4M BIT CELL MAXTRIX
X-DECODER
VCC GND
P/N: PM0239
1
REV. 2.7, NOV. 19, 2002
MX27C4111
PIN DESCRIPTION
SYMBOL A0~A17 Q0~Q14 CE OE PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Voltage Q15/A-1 VCC GND Q15(Word mode)/LSB addr. (Byte mode) Power Supply Pin (+5V) Ground Pin
BYTE/VPP Word/Byte Selection/Program Supply
TRUTH TABLE OF BYTE FUNCTION
BYTE MODE(BYTE = GND) CE H L L OE X H L Q15/A-1 X X A-1 input MODE Non selected Non selected Selected Q0-Q7 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
WORD MODE(BYTE = VCC) CE H L L OE X H L Q15/A-1 High Z High Z DOUT MODE Non selected Non selected Selected Q0-Q14 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
NOTE : X = H or L
P/N: PM0239
2
REV. 2.7, NOV. 19, 2002
MX27C4111
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C4111 When the MX27C4111 is delivered, or it is erased, the chip has all 4M bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C4111 through the procedure of programming. For programming, the data to be programmed is applied with 16 bits in parallel to the data pins. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by p r o g r a m m i n g equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This m o d e is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX27C4111. To activate this mode, the programming equipment must force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C4111, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q15) defined as the parity bit.
FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and OE = VIH (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%.
READ MODE The MX27C4111 provides page mode with 8 words/16 bytes per page. In order to get the benefit of fast page read, the user should keep chip enable(CE) low and toggle address A0~A2 in word mode or A-1~A2 in byte mode. Page Read access time(tPA) is equal to the delay from address stable to data output. It is twice as fast as normal tACC and is highly recommended.
PROGRAM INHIBIT MODE Programming of multiple MX27C4111's in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C4111 may be common. A TTL low-level program pulse applied to an MX27C4111 CE input with VPP = 12.5 ± 0.5 V will program the MX27C4111. A high-level CE input inhibits the other MX27C4111s from being programmed.
WORD-WIDE MODE With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled.
BYTE-WIDE MODE PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE at VIL, CE at VIH, and VPP at its programming voltage. With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7.
P/N: PM0239
3
REV. 2.7, NOV. 19, 2002
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