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Details, datasheet, quote on part number:MX27L1000TC-15
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Datasheet text preview:
MX27L1000
FEATURES
1M-BIT [128Kx8] LOW VOLTAGE OPERATION CMOS EPROM · Operating current: 20mA @3.6V, 5MHz · Standby current: 10uA · Package type:
32 pin plastic DIP 32 pin SOP 32 pin TSOP 32 pin PLCC
· · · · · ·
128K x 8 organization Wide power supply range, 2.7V DC to 3.6VDC +12.5V programming voltage Fast access time:90/120/150/200/250 ns Totally static operation Completely TTL compatible
GENERAL DESCRIPTION
The MX27L1000 is a 1M-bit, One Time Programmable Read Only Memory. It isorganized as 128K words by 8 bits per word, opeates from a single 2.7 to 3.6 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requirin a single pulse. For programming outside from the system, existing EPROM programmers may be used. The MX27L1000 supports a intelligent fast programming algorithm which can result in programming time of less than thirty seconds. This EPROM is packaged in industry standard 32 pin dual-in-line packages,32 lead SOP , 32 lead PLCC, and 32 lead TSOP packages.
PIN CONFIGURATIONS
32 PDIP/SOP
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC PGM NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
32 PLCC
PGM VCC VPP A12 A15 A16 NC
BLOCK DIAGRAM
CE PGM OE CONTROL LOGIC OUTPUT BUFFERS Q0~Q17
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
30 29
A14 A13 A8 A9
. . . A0~A16 ADDRESS INPUTS . . . . . VCC GND VPP Y-DECODER . . . . . . . . Y-SELECT
MX27L1000
9
MX27L1000
25
A11 OE A10 CE
X-DECODER
1M BIT CELL MAXTRIX
13 14
17
21 20
Q7
Q1
Q2
GND
Q3
Q4
Q5
Q6
PIN DESCRIPTION
32 TSOP
A11 A9 A8 A13 A14 NC PGM VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
SYMBOL A0~A16 Q0~Q7 CE OE PGM VPP NC VCC GND
PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Programmable Enable Input Program Supply Voltage No Internal Connection Power Supply Pin Ground Pin
MX27L1000
P/N: PM0238
1
REV. 3.7, NOV. 19, 2002
MX27L1000
FUNCTIONAL DESCRIPTION
AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5° ambient temperature range C that is required when programming the MX27L1000. To activate this mode, the programming equipment must force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27L1000, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit.
THE PROGRAMMING OF THE MX27L1000 When the MX27L1000 is delivered, or it is erased, the chip has all 1M bits in the "ONE" or HIGH state. "ZERO" are loaded into the MX27L1000 through the procedure of programming. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. VCC must be applied simultaneously or before VPP, and r e m o v e d simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device.
FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the PGM input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%.
READ MODE The MX27L1000 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tQE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.
PROGRAM INHIBIT MODE Programming of multiple MX27L1000s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27L1000 may be common. A TTL low-level program pulse applied to an MX27L1000 CE input with VPP = 12.5 ± 0.5 V and PGM LOW will program that MX27L1000. A high-level CE input inhibits the other MX27L1000s from being programmed.
STANDBY MODE The MX27L1000 has a CMOS standby mode which reduces the maximum VCC current to 10 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27L1000 also has a TTL-standby mode which reduces the maximum VCC current to 0.25mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE and CE at VIL, PGM at VIH, and VPP at its programming voltage.
P/N: PM0238
2
REV. 3.7 , NOV. 19, 2002
MX27L1000
TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
MODE SELECT TABLE
PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIL VIH VCC ± 0.3V VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL X VIL VIL PGM X X X X VIL VIH X X X A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP VCC VCC VCC VCC VPP VPP VPP VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z C2H 0EH
NOTES: 1. VH = 12.0 V ± 0.5 V 2. X = Either VIH or VIL 3. A1 - A8 = A10 - A16 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming.
P/N: PM0238
3
REV. 3.7 , NOV. 19, 2002
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