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Details, datasheet, quote on part number:MX28F2000PQC-90C4
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Datasheet text preview:
MX28F2000P
2M-BIT [256K x 8] CMOS FLASH MEMORY FEATURES
· 262,144 bytes by 8-bit organization · Fast access time: 70/90/120 ns · Low power consumption 50mA maximum active current 100uA maximum standby current · Programming and erasing voltage 12V ± 5% · Command register architecture Byte Programming (15us typical) Auto chip erase 5 seconds typical (including preprogramming time) Block Erase · Optimized high density blocked architecture Four 4-KB blocks (Top) Fourteen 16-KB blocks Four 4-KB blocks (Bottom) · Auto Erase (chip & block) and Auto Program DATA polling Toggle bit · 10,000 minimum erase/program cycles · Latch-up protected to 100mA from -1 to VCC+1V · Advanced CMOS Flash memory technology · Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts · Package type: 32-pin plastic DIP 32-pin PLCC 32-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX28F2000P is a 2-mega bit Flash memory organized as 256K bytes of 8 bits each. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F2000P is packaged in 32-pin PDIP, PLCC and TSOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX28F2000P offers access times as f a s t as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX28F2000P has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functiona l i t y with in-circuit electrical erasure and programming. The MX28F2000P uses a command r e g i s t e r to manage this functionality, while m a i n t a i n i n g a standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase a n d programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming o p e r a t i o n s produces reliable cycling. The MX28F2000P uses a 12.0V ± 5% VPP supply to perform the Auto Program/Erase algorithms. T h e highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
P/N: PM0380
1
REV. 1.5, OCT 29, 1998
MX28F2000P
MX28F2000P Block Address and Block Structure
A17~A0 3FFFFH 3F000H 3EFFFH 3E000H 3DFFFH 3D000H 3CFFFH 3C000H 3BFFFH 38000H 37FFFH 34000H 33FFFH 30000H 2FFFFH 2C 2B 28 27 24 23 0 F 0 F 0 F 0 F 0 F 0 F 0H FH 0H FH 0H FH 4-K byte 4-K byte 4-K byte 4-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 16-K byte 4-K byte 4-K byte 4-K byte 4-K byte
20000H 1FFFFH 1C000H 1BFFFH 1 1 1 1 8 7 4 3 0 F 0 F 0 F 0 F 0H FH 0H FH
10000H 0FFFFH 0C000H 0BFFFH 08000H 07FFFH 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 01000H 00FFFH 00000H
P/N: PM0380
2
REV. 1.5, OCT 29, 1998
MX28F2000P
PIN CONFIGURATIONS
32 PDIP
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
TSOP (TYPE 1)
A11 A9 A8 A13 A14 A17 WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
MX28F2000P
MX28F2000P
(NORMAL TYPE)
VCC
VPP
32 PLCC
A12 A15 A16 4
A17
WE
1
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
32
30 29
A14 A13 A8 A9
9
MX28F2000P
25
A11 OE A10 CE
13 14 Q1 Q2 VSS
17 Q3 Q4 Q5
21 20 Q6
Q7
OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
MX28F2000P
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 A14 A17 WE VCC VPP A16 A15 A12 A7 A6 A5 A4
(REVERSE TYPE)
PIN DESCRIPTION:
SYMBOL A0~A17 Q0~Q7 CE OE WE VPP VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write enable Pin Program Supply Voltage Power Supply Pin (+5V) Ground Pin
P/N: PM0380
3
REV. 1.5, OCT 29, 1998
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