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Details, datasheet, quote on part number:MX29F022BPC-12
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Datasheet text preview:
MX29F022/022N
2M-BIT[256K x 8]CMOS FLASH MEMORY
FEATURES
· 262,144x 8 only · Fast access time: 55/70/90/120ns · Low power consumption
-30mA maximum active current -1uA typical standby current@5MHz Programming and erasing voltage 5V±10% Command register architecture -Byte Programming (7us typical) -Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3) Auto Erase (chip & sector) and Auto Program -Automatically erase any combination of sectors or the whole chip with Erase Suspend capability. -Automatically programs and verifies data atspecified address Erase Suspend/Erase Resume -Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
· Status Reply · · · ·
-Data polling & Toggle bit for detection of program and erase cycle completion. Chip protect/unprotect for 5V only system or 5V/12V system 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1 to VCC+1V Boot Code Sector Architecture -T = Top Boot Sector -B = Bottom Boot Sector Hardware RESET pin -Resets internal state machine to read mode Low VCC write inhibit is equal to or less than 3.2V Package type: -32-pin PDIP -32-pin PLCC -32-pin TSOP (Type 1) 20 years data retention
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GENERAL DESCRIPTION
The MX29F022T/B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits only. MXIC's Flash memories offer the most cost-effective and reliable read/ w r i t e non-volatile random access memory.The MX29F022T/B is packaged in 32-pin PDIP, PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29F022T/B offers access time as fast as 55ns, allowing operation of high-speed microproc essors without wait states. To eliminate bus contention, the MX29F022T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F022T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels dur ing erase and programming, while maintaining maximum EPROM compatibility. M X I C ' s Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low in t e r n a l electric fields for erase and programming operations produces reliable cycling. The MX29F022T/ B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
1
MX29F022/022N
PIN CONFIGURATIONS
32 PDIP
NC on MX29F022NT/B
A11 A9 A8 A13 A14 A17 WE VCC RESET A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
32 TSOP (TYPE 1)
RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
MX29F022T/B
(NC on MX29F022NT/B)
MX29F022T/B
(NORMAL TYPE)
32 PLCC
NC on MX29F022NT/B
RESET
VCC
A12
A15
A16
A17
WE
SECTOR STRUCTURE
A14 A13 A8 A9
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
30 29
A17~A0 3FFFFH 3BFFFH
16 K-BYTE (BOOT SECTOR) 8 K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE
9
MX29F022T/B
25
A11 OE A10 CE
39FFFH 8 37FFFH 2FFFFH 64 1FFFFH 64 0FFFFH 64 00000H 32
13 14
17
21 20
Q7
Q1
Q2
VSS
Q3
Q4
Q5
Q6
PIN DESCRIPTION:
A17~A0
MX29F022T Sector Architecture
SYMBOL A0~A17 Q0~Q7 CE WE RESET OE VCC GND
PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Hardware Reset Pin/Sector Protect Unlock Output Enable Input Power Supply Pin (+5V) Ground Pin
3FFFFH 64 2FFFFH 64 1FFFFH 0FFFFH 07FFFH 05FFFH 03FFFH 00000H 8 8 K-BYTE K-BYTE 64 32 K-BYTE K-BYTE K-BYTE K-BYTE
16 K-BYTE (BOOT SECTOR)
MX29F022B Sector Architecture
P/N:PM0556 REV. 1.1, JUN. 14, 2001
2
MX29F022/022N
Block Diagram
CONTROL CE OE WE RESET INPUT LOGIC
WRITE PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM)
STATE MX29F022T/B FLASH ARRAY ARRAY SOURCE HV REGISTER
X-DECODER
ADDRESS LATCH A0-A17 AND BUFFER
Y-DECODER
Y-PASS GATE
COMMAND DATA DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM0556
REV. 1.1, JUN. 14, 2001
3
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