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Details, datasheet, quote on part number:MX29L1611G
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Datasheet text preview:
A D V A N C E D INFORMATION
MX29L1611G
16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE FLASH EEPROM
FEATURES
· · · · · · 3.3V ± 10% for write and read operation 11V Vpp erase/programming operation Endurance: 100 cycles Fast random access time: 90ns/100ns/120ns Fast page access time: 30ns Sector erase architecture - 32 equal sectors of 64k bytes each - Sector erase time: 200ms typical · Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip - Automatically programs and verifies data at specified addresses · Status Register feature for detection of program or erase cycle completion · Low VCC write inhibit is equal to or less than 1.8V · Software data protection · Page program operation - Internal address and data latches for 64 words per page - Page programming time: 5ms typical · Low power dissipation - 50mA active current - 20uA standby current · Two independently Protected sectors · Package type - 42 pin plastic DIP
GENERAL DESCRIPTION
The MX29L1611G is a 16-mega bit Flash memory organ i z e d as either 1M wordx16 or 2M bytex8. The MX29L1611G includes 32 sectors of 64KB(65,536 Bytes or 32,768 words). MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29L1611G is packaged in 42 pin PDIP. The standard MX29L1611G offers access times as fast as 100ns, allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29L1611G has separate chip enable CE and, output enable (OE). MXIC's Flash memories augment EPROM functionality w i t h electrical erasure and programming. The MX29L1611G uses a command register to manage this functionality. MX29L1611G does require high input voltages for programming. Commands require 11V input to determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 100 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29L1611G uses a 11V Vpp supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC +1V.
P/N:PM0604
REV. 0.9.1, NOV. 21, 2002
1
MX29L1611G
PIN CONFIGURATIONS 42 PDIP
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
PIN DESCRIPTION
SYMBOL A0 - A19 Q0 - Q14 Q15/A-1 CE OE BYTE/VPP VCC GND PIN NAME Address Input Data Input/Output Q 1 5 ( Wo r d mode)/LSB addr.(Byte mode, for read mode only) Chip Enable Input Output Enable Input Word/Byte Selection Input, Erase/Program supply voltage Power Supply Ground Pin
P/N:PM0604
MX29L1611G
REV. 0.9.1, NOV. 21, 2002
2
MX29L1611G
BLOCK DIAGRAM
WRITE CE OE BYTE / VPP CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
MX29L1611G FLASH ARRAY ARRAY
ADDRESS Q15/A-1 A0-A19 LATCH AND BUFFER
COMMAND INTERFACE REGISTER (CIR)
X-DECODER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
SENSE AMPLIFIER
PGM DATA HV COMMAND DATA LATCH
Y-select PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM0604
REV. 0.9.1, NOV. 21, 2002
3
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