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Details, datasheet, quote on part number:MX29L1611PC-12
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Datasheet text preview:
PRELIMINARY
MX29L1611
16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM
FEATURES
· Regulated voltage range 3.0 to 3.6V write, erase and read(MX29L1611-75/10/12) · Fast random access/page mode access time: 75/ 30ns, 100/30ns, 120/30ns. · Full voltage range 2.7 to 3.6V write, erase and read (MX29L1611-90) · Fast random access/page mode access time: 90/ 35ns · Endurance: 10,000 cycles · Page access depth: 16 bytes/8 words, page address A0, A1, A2 · Sector erase architecture - 32 equal sectors of 64k bytes each - Sector erase time: 200ms typical · Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip with Erase Suspend capability - Automatically programs and verifies data at specified addresses Status Register feature for detection of program or erase cycle completion Low VCC write inhibit < 1.8V Software and hardware data protection Page program operation - Internal address and data latches for 128 bytes/64 words per page - Page programming time: 5ms typical Low power dissipation - 50mA active current - 20uA standby current Two independently Protected sectors Industry standard surface mount packaging - 44 lead SOP, 48 TSOP(I)
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GENERAL DESCRIPTION
The MX29L1611 is a 16-mega bit pagemode Flash memory organized as either 1M wordx16 or 2M bytex8. The MX29L1611 includes 32 sectors of 64KB(65,536 Bytes or 32,768 words). MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory and fast page mode access. The MX29L1611 is packaged 44-pin SOP and 48-TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29L1611 offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29L1611 has separate chip enable CE, output enable (OE), and write enable (WE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29L1611 uses a command register to manage this functionality. To allow for simple in-system reprogrammability, the MX29L1611 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 10,000 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29L1611 uses a 2.7V~3.6V VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.
P/N:PM0511
REV. 2.5, NOV. 21, 2002
1
MX29L1611
PIN CONFIGURATIONS
44 SOP(500mil)
WE A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WP A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
PIN DESCRIPTION
SYMBOL A0 - A19 Q0 - Q14 Q15/A-1 CE OE WE WP* BYTE VCC GND
*Only for 44-SOP
PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr.(Byte mode) Chip Enable Input Output Enable Input Write Enable Input Sector Write Protect Input Word/Byte Selection Input Power Supply Ground Pin
48 TSOP (NORMAL TYPE)
BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 GND WE A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC VCC NC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND GND
MX29L1611
MX29L1611 (Normal Type)
P/N:PM0511
REV. 2.5, NOV. 21, 2002
2
MX29L1611
BLOCK DIAGRAM
WRITE WE OE WP BYTE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
MX29L1611 FLASH ARRAY ARRAY
ADDRESS Q15/A-1 A0-A19 LATCH AND BUFFER
COMMAND INTERFACE REGISTER (CIR)
X-DECODER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
SENSE AMPLIFIER
PGM DATA HV COMMAND DATA LATCH
Y-select PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM0511
REV. 2.5, NOV. 21, 2002
3
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