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Details, datasheet, quote on part number:MX29LV800TTI-70G
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Datasheet text preview:
MX29LV800T/B & MX29LV800AT/AB
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
· Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase operation completion. · Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors. · C F I (Common Flash Interface) compliant (for MX29LV800AT/AB) - Flash device parameters stored on the device and provide the host system to access · 100,000 minimum erase/program cycles · Latch-up protected to 100mA from -1V to VCC+1V · Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector · Package type: - 44-pin SOP - 48-pin TSOP - 48-pin CSP (8x9mm for MX29LV800T/B; 6x8mm for MX29LV800AT/AB) · Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash · 20 years data retention ister allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV800T/B & MX29LV800AT/AB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. Part Name Difference MX29LV800T/B 1.Without CFI compliant 2. CSP dimension:8x9mm MX29LV800AT/AB 1.With CFI compliant 2. CSP dimension:6x8mm
REV. 2.2, APR. 11, 2003
FEATURES
· Extended single - supply voltage range 2.7V to 3.6V · 1,048,576 x 8/524,288 x 16 switchable · Single power supply operation - 3.0V only operation for read, erase and program operation · Fast access time: 70/90ns · Low power consumption - 20mA maximum active current - 0.2uA typical standby current · Command register architecture - Byte/word Programming (9us/11us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15) · Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address · Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. · Status Reply - Data polling & Toggle bit for detection of program and erase operation completion.
GENERAL DESCRIPTION
The MX29LV800T/B & MX29LV800AT/AB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV800T/B & MX29LV800AT/AB is packaged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV800T/B & MX29LV800AT/AB offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To elimin a t e bus contention, the MX29LV800T/B & MX29LV800AT/AB has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV800T/B & MX29LV800AT/AB uses a command register to manage this functionality. The command regP/N:PM0709
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MX29LV800T/B & MX29LV800AT/AB
PIN CONFIGURATIONS
44 SOP(500 mil)
RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
PIN DESCRIPTION
SYMBOL A0~A18 Q0~Q14 Q15/A-1 CE WE BYTE RESET OE RY/BY VCC GND PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr(Byte mode) Chip Enable Input Write Enable Input Word/Byte Selection input Hardware Reset Pin Output Enable Input Ready/Busy Output Power Supply Pin (2.7V~3.6V) Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
MX29LV800T/B, MX29LV800AT/AB
MX29LV800T/B, MX29LV800AT/AB
48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down (8mm x 9mm for MX29LV800T/B and 6mm x 8mm for MX29LV800AT/AB) A 6 5 4 3 2 1 A13 A9 WE RY/BY A7 A3 B A12 A8 RESET NC A17 A4 C A14 A10 NC A18 A6 A2 D A15 A11 NC NC A5 A1 E A16 Q7 Q5 Q2 Q0 A0 F BYTE Q14 Q12 Q10 Q8 CE G H
Q15/A-1 GND Q13 Vcc Q11 Q9 OE Q6 Q4 Q3 Q1 GND
REV. 2.2, APR. 11, 2003
P/N:PM0709
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MX29LV800T/B & MX29LV800AT/AB
BLOCK STRUCTURE TABLE 1: MX29LV800T/MX29LV800AT SECTOR ARCHITECTURE
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Size Byte Mode Word Mode 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 32Kbytes 8Kbytes 8Kbytes 16Kbytes 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 16Kwords 4Kwords 4Kwords 8Kwords Address range Byte Mode (x8) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-F7FFFh F8000h-F9FFFh FA000h-FBFFFh FC000h-FFFFFh Word Mode (x16) 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7BFFFh 7C000h-7CFFFh 7D000h-7DFFFh 7E000h-7FFFFh 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 Sector Address A18 A17 A16 A15 A14 A13 A12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X 0 0 1 X X X X X X X X X X X X X X X X 0 1 X
Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.
P/N:PM0709
REV. 2.2, APR. 11, 2003
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