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Details, datasheet, quote on part number:MX88L60UC
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Datasheet text preview:
BRIEF
MX88L60
DUAL-MODE PC CAMERA CONTROLLER FEATURES
· Power - 3.3V with power saving control · Image Sensor Interface - 8-bit to 10-bit resolution for digital image raw data input - Support imager with resolution up to SVGA (800x592)with windowing mode or random-access control - Support universal serial interface for various CCD and CMOS sensors * CCD sensor: Sony , Sharp , and Panasonic * CMOS sensor: Hyundai, HP, VLSI Vision (VVL), Photobit, Biomorphic, TASC, etc. · Image Processing Unit - Complete image processing functions: * RGB Bayer CFA color interpolation * Black reference * Defect concealment * Flare and black level correction * Brightness and contrast control * Edge enhancement * Color correction * Gamma correction * RGB to YUV color space conversion * Color saturation control * False color suppression * Image sub-sampling - Programmable 5(H) x 5(V) zones with programmable size for image statistical calculation to facilitate automatic exposure control and automatic white balance - Support focus-assisting signaling control (with Melody IC interface) · Video Compression Unit - High quality and high performance proprietary compression algorithm for live video capture and transferring * 30 fps for CIF (352x288) * 10~15 fps for VGA (640x480) · Memory Control Interface - Support both EDO DRAM (256Kx16) x1 or SDRAM (1Mx16) x1 or x2 - Support NAND-type Flash memory (8Mb,16Mb,32Mb,64Mb) x1 or x2 - Support serial Flash memory (MX25L4004, 4Mb) x1, x2,x3 or x4 - Support Compact Flash card and Smart Media card. - Support NDR-type Flash memory (16Mb,32Mb,64Mb) - Support EEPROM for sensor information - Support Flash memory format function, controlled by PC software
P/N: PM0743
· PC Interface - High speed USB interface with embedded transceiver - UART interface with external transceiver, for best backward compatibility · Portable Mode Additional Features - Embedded 8051 micro-controller - Support external ROM code storage at Flash memory or EPROM - Embedded real-time-clock (RTC) for time stamp * Adjusted by PC software * On-System programming capability at portable mode - Support monochrome TN LCD for information display. The logos include: * Date * Time * Number of pictures left: 2 or 3 digits * Flash light status: ON/OFF/AUTO * Self Timer: On, Off, and Flash when push the snap shot button * Battery status: High, low, and empty * Continuous shots: On and Off * Quality (compression rate): Best, Better, Good (total 8 classes actually) * Image size: Full, 1/2 - Support self timer function - Support melody IC for singling control when * Initialization * Self timer * Snap shot * Low battery * Failure shot - Support flashlight charge control · Miscellaneous - 48 MHz system clock operation - Dedicated sensor clock input(optional) - Built in 27 general-purpose I/O pins - 160 pin LQFP
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REV. 2.5B, AUG. 18, 2000
MX88L60
GENERAL DESCRIPTION
The MX88L60 is a general-purpose controller for dualmode (tethered and portable) PC cameras and toy cameras. The MX88L60 contains all the necessary hardware supports, like image sensor control and interface, i m a g e capture and processing, proprietary video compression, memory control, USB and UART interface, embedded micro-controller and general-purpose I/Os. With the intensive hardware and associated software supports, it is an ideal solution for a tethered digital video camera, which can capture real-time live video for entertainment or videoconference applications. For still image capture, the MX88L60 can also function as a controller for low-cost digital still camera (DSC) or toy camera. With Flash memory interface support and powersaving control, it can make the system work on battery power for portable purpose.
PIN CONFIGURATION
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PSEN_B PALE RST_B EA CLK48O CLK48I VDD GPIO 25 GPIO 24 GPIO 23 GPIO 22 GPIO 21 CLKSNO CLKSN GPIO 20 GPIO 19 GPIO 18 GPIO 17 GND GPIO 16 GPIO 15 GPIO 14 GPIO 13 GPIO 12 GND VDD SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 ADCK VDD PBLK XCLPOB
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 GND P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 GND VDD P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 GND VDD D+ DGND
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
MX88L60
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
XCLPDM XRS GND XSHD XSHP XSG2 XSG1 XV3/HRO XV2/FRO XV1/HRI XV0FRI XSUB H2 H1 RG FQ7 FQ6 FQ5 FQ4 FQ0 VDD FQ1 FQ2 FQ3 GND VDD GND FCEB_B FCEA_B FRE_B FRB_B FCLE FALE FWE_B FWP_B DA4 DA5 DA6 DA7 DA8
VDD GND CLK32KI CLK32KO GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VDD GND DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DWE_B DCAS_B DRAS_B SDCSA_B SDCSB_B SDCKE VDD SD_CLK GND DOE_B DBANK DA10 DA0 DA1 DA2 DA3 DA9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P/N: PM0743
REV. 2.5B, AUG. 18, 2000
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MX88L60
Pin Numbers in Numerical Sequence
Name VDD GND CLKRTCI CLKRTCO GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VDD GND DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DWE_B DCAS_B DRAS_B SDCSA_B SDCSB_B SDCKE VDD SDCLKO GND DOE_B DBANK DA10 DA0 DA1 DA2 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Type Definition 3.3V RTC crystal oscillator input, 32KHz RTC crystal output DRAM data bit 0, pull high/low, mapping to register DRAM_TYPE[0] DRAM data bit 1, pull high/low, mapping to register DRAM_TYPE[1] DRAM data bit 2, pull high/low, mapping to register DCK[0] DRAM data bit 3, pull high/low, mapping to register DCK[1] DRAM data bit 4, , pull high/low, mapping to register DCK[2] DRAM data bit 5, pull high/low, mapping to register DCK[3] DRAM data bit 6, pull high/low, mapping to register TEST[0] DRAM data bit 7, pull high/low, mapping to register TEST[1] 3.3V DRAM data bit 15, pull high/low, mapping to register TEST[9] DRAM data bit 14, pull high/low, mapping to register TEST[8] DRAM data bit 13, pull high/low, mapping to register TEST[7] DRAM data bit 12, pull high/low, mapping to register TEST[6] DRAM data bit 11, pull high/low, mapping to register TEST[5] DRAM data bit 10, pull high/low, mapping to register TEST[4] DRAM data bit 9, pull high/low, mapping to register TEST[3] DRAM data bit 8, pull high/low, mapping to register TEST[2] DRAM write enable DRAM Column address strobe DRAM Row address strobe SDRAM #0 chip select SDRAM #1 chip select SDRAM clock enable 3.3V SDRAM clock output SDRAM, ldqm, udqm, EDORAM output enable SDRAM bank select SDRAM address bit 10 DRAM address bit 0 DRAM address bit 1 DRAM address bit 2
I O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O
P/N: PM0743
REV. 2.5B, AUG. 18, 2000
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