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Part: CX28500
Category:
Communication
-> Network
-> HDLC/Frame Relay/Token-Ring
-> HDLC Link Layer Controllers
Description: Multichannel Synchronous Communications Controller
Company: Mindspeed Technologies
Datasheet: Download CX28500 datasheet File size : 1379 kB
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Datasheet text preview:
CX28500
Multichannel Synchronous Communications Controller
Data Sheet
500052D November 2002
Ordering Information
Model Number CX28 500EBG Package 35 mm TBGA Operating Temperature 4085 °C
Revision History
Revision A B C D Level -- -- -- -- Date July 2001 February 2002 July 2002 November 2002
Created. Updated to Revision B. Updated to Revision C. Updated to Revision D.
Description
© 2001, 2002, Mindspeed TechnologiesTM, a Conexant business All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies ("Mindspeed") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Mindspeed's Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Mindspeed TechnologiesTM, the MindspeedTM logo, and "Build It First"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at www.mindspeed.com which is incorporated by reference.
500052D
Mindspeed TechnologiesTM
CX28500 Multichannel Synchronous Communications Controller
The CX28500 is an advanced Multichannel Synchronous Communications Controller. Distinguishing Features 1024-channel HDLC controller It formats and deformats up to 1024 High-level Data Link Control (HDLC) channels in OSI Layer 2 protocol support a CMOS integrated circuit. CX28500 operates at Layer 2 of the Open Systems General purpose HDLC (ISO 3309) Interconnection (OSI) protocol reference model. It provides a comprehensive, highX.25 (LAPB) density solution for processing of HDLC channels for internetworking applications Frame relay (LAPF/ANSI T1.618) such as Frame Relay, Integrated Services Digital Network (ISDN), D-channel ISDN D-channel (LAPD/Q.921) signaling, X.25, Signaling System 7 (SS7), Data Exchange Interface (DXI), Inter ISLP support System Link Protocol (ISLP), and LAN/WAN data transport. Under minimal Host 32 Independent serial interfaces, which supervision, CX28500 manages table-like data structures of channel data buffers in support: Host memory by performing Direct Memory Access (DMA) of up to 1024 channels. Mixed Data Rates (combination of T1/ E1/T3/E3, etc.) as long as they do not CX28500 interfaces to 32 independent serial data streams, such as T1/E1 signals. It exceed each port's respective then transfers data across the popular 32-bit or 64-bit Peripheral Component bandwidth limitation and the overall Interface (PCI) bus to system memory at a rate up to 66 MHz. The CX28500 has an device bandwidth of 390 Mbps per aggregate data throughput of 390 Mbps. Each serial interface can be operated up to direction 32 T1/E1 data streams 13.0 MHz. Six Serial Interfaces can be operated at rates up to 52 MHz. Logical 6 HSSI interfaces (52 Mbps) channels can be mapped as any combination of Digital Signal Level 0 (DS0) time slots DC to 13.0 Mbps serial interfaces to support ISDN hyperchannels (N x 64 Kbps). Additionally, logical channels can 32 x 8.192 MHz TDM busses operate in subchanneling mode (N x 8 Kbps) by mapping a combination of DS0 time Configurable logical channels slots and/or the individual bits of a DS0 time slot (8 bits). For example, a 56 Kbps Standard DS0 (56, 64 Kbps) channel can be achieved by mapping 7 bits out of 8 possible bits in a time slot (7 x 8 Subchanneling (N x 8 Kbps) Kbps = 56 Kbps). CX28500 also includes a 32-bit expansion port for bridging the PCI Hyperchannel (N x 64 Kbps) bus to local microprocessors or peripherals. A Joint Test Action Group (JTAG) port Unchannelized mode enables boundary-scan testing to replace bed-of-nails board testing. Per-channel protocol mode selection
Functional Block Diagram
Non-FCS mode 16-bit FCS mode 32-bit FCS mode Transparent mode (unformatted data)
HOST Interface (PCI) Device Configuration Registers PCI BUS PCI Interface
Rx Line Processor
0
RSLP
RxDMA and TxDMA Tx Line Processor Serial Interface Unit (SIU) TSBUS or PCM Highway
PCI Configuration Space (Function 0)
TSLP
31
EXP BUS
JTAG
Test Access
Flow Control (CTS) Endian configuration on data Per-channel DMA buffer management Table-like data structures Variable size transmit/receive FIFO Per-channel message length check Select no length checking Select from three 14-bit registers to compare message length Direct PCI bus interface 32/64-bit, 33/66 MHz operation Bus master and slave operation PCI Version 2.1 Host back-to-back transaction over the PCI HSSI interfaces (52 Mbps) Local expansion bus interface (EBUS) 32-bit multiplexed address/data bus
Hardware Selectable TSBUS
Local BUS
500052_020
Physical Interface
of 64-bit ECC host memory power, 3.3 V CMOS operation JTAG boundary scan access port 35 mm x 35 mm 580-pin BGA
Support Low
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Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 1.2 1.3 CX28500's Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 CX28500 Serial Port Throughput Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 CX28500's Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.1 PCI--Peripheral Components Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.2 EBUS--Local Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.3 TSBUS--Time Slot Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 CX28500 Layering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 CX28500's Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 CX28500 Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.6.1 T1/T3 WAN Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.6.2 T3/E3 Frame Relay Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.6.3 128 Port DSL Access Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.6.4 SONET/SDH Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.6.5 Line Card SONET/ATM SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 CX28500 Hardware Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
1.4 1.5 1.6
1.7 1.8 1.9 1.10 1.11 1.12 1.13
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 2.3 2.4 Serial Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Line Processor (SLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 General Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-4 2-5
3
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
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