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Part: CX28560
Category:
Communication
-> Network
-> HDLC/Frame Relay/Token-Ring
-> HDLC Link Layer Controllers
Description: HDLC Controller
Company: Mindspeed Technologies
Datasheet: Download CX28560 datasheet File size : 1379 kB
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Datasheet text preview:
CX28560 HDLC Controller
Data Sheet
500031C July 2002
Ordering Information
Model Number -- Package TBGA 40 mm x 40 mm Operating Temperature 40 °C to +85 °C
Revision History
Revision A A B Level Advance Advance Advance Date December 2000 April 2001 October 2001 Description Initial release (document No. 101302A).
500031A Correction Corrected In
Formerly document No. 101302A. of technical inaccuracies for first full release.
fuzzy drawings (Chapter 8.0). Table 9-3, replaced signal names to match Pin Description. Created Table 1-13 for ONESEC signal. on preliminary characterization, updated EBUS timing specification (Section 8.2.4) and few other electrical specifications (Chapter 8.0). Corrected technical inaccuracies.
Based
C
Advance
July 2002
© 2001, Mindspeed TechnologiesTM, A Conexant Business All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies ("Mindspeed") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Mindspeed's Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Mindspeed TechnologiesTM, the MindspeedTM logo, and "Build It First"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at www.mindspeed.com which is incorporated by reference.
500031C
Mindspeed TechnologiesTM
Advance Information
Advance Information
This document contains information on a product under development. The parametric information contains target parameters that are subject to change.
CX28560 HDLC Controller
The CX28560 is an advanced Multichannel Synchronous Communications Controller Distinguishing Features 2047-channel HDLC controller (MUSYCCTM) that formats and deformats up to 2047 HDLC channels in a CMOS OSI Layer 2 protocol support integrated circuit. MUSYCC operates at Layer 2 of the Open Systems Interconnection 32-bit full duplex standard POS-PHY Level (OSI) protocol reference model and provides a comprehensive, high-density solution 3 bus for processing HDLC channels for inter-networking applications.
Aggregate
All packet data passed between the system and the CX28560 is passed across the POS-PHY interface (POS-PHY). The POS-PHY operates in packet mode as a 32-bit wide point-to-point interface at 100 MHz. Data is transferred in fragments of userconfigurable length (minimum 32 bytes per fragment). The CX28560 supports a PCI interface for initial configuration as well as to perform dynamic activation and deactivation of channels. In addition, the CX28560's configuration and performance monitoring counters can be read over the PCI interface. The scheduling system for the receive and transmit data flow is based on the unique FlexiframeTM algorithm. Flexiframe enables efficient memory utilization and provides support for various channels operating at extremely different rates. Flexiframe allows dynamic resizing of every channel's rate without affecting the other channels. The order in which message fragments are transferred across the POS-PHY is fixed by the Flexiframe structure, each fragment having been tagged with a 4-byte fragment header. The fragment header contains the channel number and relevant status information. A dedicated 8-bit bus provides the system the necessary feedback to determine the amount of data contained in each channel's transmit buffers. This is achieved by the CX28560 sending requests to the system for more transmit data. In the receive direction, the CX28560 operates autonomously without any need for system intervention or guidance.
Functional Block Diagram
Por t 0 Bi-directional 32 b, 100 MHz POS-PHY Bus (Data) Unit-directional 8 b 100 MHz Tx FlowConductor Bus Internal Buffer Controllers Rx and Tx Serial Line Processors Rx and Tx Serial Interface Units Por t 1 . . . Por t 31 POS-PHY I/F Interrupt Controller
Flexiframe Scheduler
Host Service Unit Miscellaneous JTAG etc.
PCI I/F
EBUS Bridge
bandwidth of 700 Mbps full duplex 32 bits, 33 MHz PCI 2.2 bus interface for configuration and monitoring Dedicated feedback bus for Tx buffers fill level 32 independent serial interfaces support: T1 data stream N * 64 Kb/s data stream TSBUS interfaces Unchannelized data stream Configurable logical channels Standard DS0 (56, 64 Kbps) Hyperchannel (N x 64) Channels' bit rate can be dynamically changed. Per channel protocol mode selection Per-channel message length check Select no length checking Select from three 14-bit registers to compare message length HDLC maximum packet length 16,384 bytes 3 separate HDLC modes, configurable per channel: no FCS 16-bit FCS 32-bit FCS Transparent (not HDLC) mode Autonomous Rx operation and arbitration between the channels Selectable endian configuration for control information (PCI) Per-channel buffer management Full set of 10 performance monitoring counters per channel Transfer of partial HDLC messages over the POS-PHY interface Low power, 1.8 volt core, 3.3 volt I/O, CMOS operation. Local expansion bus interface (EBUS) for accessing non-PCI components (framers, LIUs) JTAG boundary scan access port 40 mm TBGA package
PCI Bus 2.2
Expansion Bus
500031C
Mindspeed TechnologiesTM
Advance Information
iii
CX28560 Data Sheet
The CX28560 supports four serial port modes: Conventional Channelized, Conventional Unchannelized, Conventional T1, and TSBUS. In TSBUS mode, the CX28560 supports a special Mindspeed proprietary interface: the TSBUS (Time Slot BUS). The TSBUS allows for mapping of all tributary signals to time slots for a transmission to external devices, such as Mindspeed's BAM (Broadband Access Multiplexer) device family. The TSBUS interface consists of two serial interfaces: a 51.84 MHz payload interface and a 12.96 MHz overhead interface. Payload of tributary signals is mapped to time slots on the payload bus allowing for a transmission of the following signals' payload:
x DS1, VT1.5, or VC-11 signals x E1, VT2.0, or VC-12 signals 1 x DS3, E3, or STS-1 signal
28 21
Overhead information including SONET/SDH/PDH overhead and control information is transmitted in time slots on the overhead TS-Bus interface. The first 12 ports of the CX28560, when configured in TSBUS mode, also support DS0 extraction.
500031C
Mindspeed TechnologiesTM
Advance Information
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Contents
Figures Tables
1.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv
External Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 CX28560 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1.1 CX28560 Serial Port Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1.2 CX28560 Serial Port Throughput Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1.3 TSBUS--Time Slot Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 System-Side Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1 POS-PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1.1 POS-PHY Data Interface--CX28560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1.2 Transmit FlowConductor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.2 Expansion Bus (EBUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.3 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Applications Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7.1 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7.2 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 CX28560 Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.8.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
1.3 1.4 1.5 1.6 1.7
1.8
500031C
Mindspeed TechnologiesTM
Advance Information
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