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Part: CX29610-12P
Category:
Communication
-> Network
-> SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3)
-> Framers/Mappers/PHYs
Description:
Company: Mindspeed Technologies
Datasheet: Download CX29610-12P datasheet File size : 1379 kB
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Datasheet text preview:
CX29610 OptiPHYTM - M622 STS-12/4x STS-3 SONET/SDH Multiplexer
Data Sheet
500243A March 2002
Ordering Information
Model Number CX29610-12P Package 27 mm PBGA Operating Temperature 40 °C to 85 °C
© 2001, 2002, Mindspeed TechnologiesTM, a Conexant business
All Rights Reserved. Infor mation in this document is provided in connection with Mindspeed Technologies ("Mindspeed") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Mindspeed's Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Mindspeed TechnologiesTM, the MindspeedTM logo, and "Build It First"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at www.mindspeed.com which is incorporated by reference.
500243A
Mindspeed TechnologiesTM
CX29610
OptiPHYTM - M622 STS-12/4x STS-3 SONET/SDH Multiplexer
CX29610 is a highly integrated, multiport chip that provides SONET/SDH processing and multiplexer/demultiplexer functions for a single STS-12/STM-4 data stream or four STS-3/STM-1 data streams. All mappings are compliant with SONET/SDH standards including Bellcore GR-253, ANSI T1.105, and ITU G.707. Each port supports full-duplex overhead processing of SONET/SDH data streams for section, line, and path layers, framing, scrambling/descrambling, alarm detection/insertion, and BIP error monitoring. Serial interfaces for Section and Line DCC's are also provided. Automatic Protection Switching (APS) is supported via full K1/K2 byte access with Bit Error Rate (BER) calculations done in hardware. This APS support is also fully compatible with Conexant's APS protocol stack software package. The line-side interface is compliant with industry standard LVPECL serial interface transceivers. The drop-side interface is a byte-wide data and clock interface for STS-3 streams in Conexant's SONET Interleave interface (SI-Bus) format. This interface provides the ability to pass payload information to nearby processing elements in either STS-1, VC-4 or VC-3 format. An additional serial data channel for each port is provided to support downstream processing (i.e., HDLC). Continued
Distinguishing Features
· Processes combinations of STS-12, STS-3 payload framing/multiplexing for: 1x STS-12/STM-4 4x STS-3/STM-1 Glueless connectivity to the CX29503/CX29513 and CX28500/CX28560 devices. Automatic Protection Switching Bit Error Rate calculations performed in hardware User-programmable signal fail and signal degrade thresholds Device Driver reference source code available Generates/terminates section, line, and path overhead.
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· ·
Continued Functional Block Diagram
Serial LRxData +/-_1 LSigDet_1 PECL IF Parallel to Serial LTxData +/-_1 Port 1 STS-3/12 (STM-1/4) TX Framer CDR to Parallel STS-3/12 (STM-1/4) RX Framer STS-12 to 4xSTS-3 DEMUX
SOH/ LOH Pointer Processor POH SOH/ LOH Pointer Processor POH
SRxData_1[7:0] SI-BUS Interface Port 1 STxData_1[7:0]
Serial LRxData +/-_2 LSigDet_2 PECL IF Parallel to Serial LTxData +/-_2 CDR to Parallel
STS-3 RX Framer
SOH/ LOH Pointer Processor POH
SRxData_2[7:0] SI-BUS Interface Port 2
STS-3 TX Framer
SOH/ LOH Pointer Processor POH
STxData_2[7:0]
STS-3 CrossConnect
Port 2
Serial LRxData +/-_3 LSigDet_3 PECL IF Parallel to Serial LTxData +/-_3 CDR to Parallel
STS-3 RX Framer
SOH/LOH insert POH insert
SRxData_3[7:0] SI-BUS Interface Port 3
STS-3 TX Framer
SOH/LOH POH insert
STxData_3[7:0]
STS-12 Port 3 to 4xSTS-3 MUX Serial
insert
LRxData +/-_4 LSigDet_4 PECL IF
CDR
to Parallel
STS-3 RX Framer
SOH/LOH insert
POH insert
SRxData_4[7:0] SI-BUS Interface Port 4
Parallel to Serial
STS-3 TX Framer
SOH/LOH insert
POH insert
STxData_4[7:0]
LTxData +/-_4 Port 4
Transmit Clock Synthesizer
Microprocessor Interface
Section/Line DCC Interface
Section/Line Orderwire Interface
J TA G Interface
500243A
Continued from Front
An 8-bit microprocessor interface is provided for access to control and status registers. This interface provides direct conectivity to the Conexant EBUS and the Motorola MPC860 microprocessor interfaces. A full complement of status monitoring, alarm indications, and error counters is provided with maskable interrupts for all status indications. CX29610 is fully compatible with CX29503 Conexant's Broadband Access Multiplexer (BAM) which is a highly integrated STS-1/DS3/E3/DS1/E1/VT1.5 Mapper/Framer. This chipset provides multiplexing solutions from T1/E1 up through STS-12 through either PDH, SONET, or SDH hierarchies.
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Mindspeed TechnologiesTM
500243A
Continued Distinguishing Features
· · · · Embedded clock and data recovery Alarm indicators, status monitoring, and error counters Provides serial LVPECL interfaces to optical transceivers 8-bit microprocessor interface for control and status compatible with the Conexant EBUS and Motorola MPC860 interfaces Interrupt suppression to suppress low level interrupts when high level interrupts occur Low-power 3.3 V process with 5 V tolerant I/O JTAG and boundary scan test support
Overhead Processing
Section Overhead · Monitors A1/A2 framing and recovers byte-alignment from incoming serial data Provides 64-byte transmit and receive buffers for section trace messages Generates and checks errors for B1 BIP Serial interface for D1-D3 Section DCC Section SEF processing Codec compatible E1 orderwire serial interface
Payload Mapping/Demapping
· · · SONET: STS-1 -> STS-1 SPE SDH: AU-4 -> VC-4 -> TUG-3 -> TU-3 SDH: AU-3 -> VC-3
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Drop Interface
· · Conexant SONET Interleave interface (SI-Bus) 8-bit data, clock, and sync interfaces for STS-1, VC-4, or VC-3 payloads
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· · · ·
· ·
Control and Status
· · · 8-bit register interface Summary interrupts for various line conditions Interrupt supression of low level alarms based on high level alarm conditions (i.e., LOS). Error insertion capability "One-second" status and counters latching for alarm/error detection and performance monitoring Derives 1-sec output from 8 kHz clock input
Applications
· · · Access Concentrators Edge Routers SONET Cross Connects
Line Overhead · · · · · · Full pointer processor for tributaries Generates and checks errors for B2 BIP Serial interface for D4-D12 Line DCC Register access for S1 Sync byte Line AIS, RDI, REI processing Codec compatible E2 orderwire serial interface
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Line Interface
· · · · Industry standard serial LVPECL interface to external transceivers Transmit clock synthesis Built-in receive clock and data recovery Monitors receive data for LOS conditions
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Path Overhead · Provides 64-byte transmit and receive buffers for path trace messages Generates and checks errors for B3 BIP Generates/monitors for appropriate C2 signal label Path AIS, RDI processing
Electro-mechanical
· · · · Power dissipation under 2.3 W 3.3 V power supply 416 pin 27 mm PBGA Industrial operating temperature range (-40 șC to 85 șC) with airflow
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500243A
Mindspeed TechnologiesTM
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