|
Details, datasheet, quote on part number:GT-48001A
| |
| Part: | GT-48001A |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => Controllers |
| Description: | Switched Ethernet Controller For 10BaseX |
| Company: | Marvell Semiconductor, Inc. |
| Datasheet: | Download GT-48001A datasheet File size : 1265 kB |
| Request For quote: | Find where to buy GT-48001A
|
| |
Datasheet text preview:
Switched Ethernet Controller for 10BaseX FEATURES
· Single-chip, low cost, Switched Ethernet Controller - Provides packet switching functions between 8 onchip Ethernet ports and the PCI expansion port - Switch expansion via 1Gbps PCI bus · GalNet Architecture Family Member - Advanced distributed switching architecture - Connects seamlessly to other GalNet Family Devices - GT-48002A 100BaseX and GT-48003 100VGAnyLAN devices available · Incorporates eight 802.3 compliant Ethernet ports - 10Mbps half-duplex or full-duplex 20Mbps Ethernet for each port - Serial mode selectable per port: 10Base-T, 10Base-FL, AUI, and NRZ Synchronous · All digital logic on-chip for each port - Media Access Control (MAC) - Manchester encoder/decoder - Link integrity, Partition - Automatic polarity detection and correction - Dual 32-byte FIFOs for receive and transmit - 7 LEDs for Link Status, Receive, Transmit, Collision, Forward Unknown Packets, Port Sniffer, and Half/Full Duplex - CRC generation for CPU generated packets · High-Performance Distributed Switching Engine - Performs forwarding and filtering at full wire speed - 14,880 packets/sec on each Ethernet port - Flexible software or hardware intervention in packet routing decisions · Supports `Store and Forward' switching approach - Low last-bit in to first-bit out delay - Allows bridging between higher/lower speed interfaces (Fast Ethernet, ATM, WAN)
P C I Bus
GT-48001A
Preliminary Revision 1.6 12/29/97
Please contact Galileo Technology for possible updates before finalizing a design.
· Advanced address recognition - Intelligent address recognition mechanism enables forwarding rate at full wire speed - Self-learning mechanism - Supports up to 8K Unicast addresses and unlimited Multicast/Broadcast addresses - Broadcast storm rate filtering · Direct support for packet buffering - Glueless interface to 1 or 2Mbyte of 60ns EDO DRAM - Up to 1K buffers, 1536-bytes each, dynamically allocated to the receive and PCI ports · PCI Rev 2.1 interface for switch expansion and management CPU connection - Up to 10 GT-48001A devices per PCI bus without PCI-to-PCI bridging - Up to 32 GalNet devices in a single switch - Standard CPU connection for management - Simple interface to other networking interfaces (ATM, FDDI, etc.) · Extensive network management support - Repeater MIB and PCI counters - Address aging support - Hardware assist for Spanning Tree algorithm - RMON Station-to-Station connectivity matrix - CPU access to Address Table - Ability to define static addresses - Monitoring (sniffer) mode · HP-EASE Packet sampling management technology - Takes "snapshots" of packets at programmable intervals - Allows for the implementation of HP-EASE or sampled RMON with low-cost CPUs · 208 pin PQFP package
C o n fig u ra tio n Registers PC I Ad d r e s s Table Pa c k e t Buffers S e r ial Sw itc h in g G AL N ET M is c e lla n e ou s Sta tis tic s Counters PC I Counters 8 x MIB Counters Sw itc h in g E n g in e DM A Se lf- Le a r n in g & Ad d re s s R e c o g n itio n E n g in e DRA M C o n tro ller D a ta Ad d re s s C o n tro l PC I Bus Controller G AL N ET C o n tro ller
Sn iffe r C o n tro l
In te rv e n tio n M od e C o n tro l
Fra m e C o n tro ller
DM A
R M O N FIFO C o n t ro l
C o n t ro l
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
Tx Rx FIF O FIFO
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8 0 2. 3 MAC
8x L ED C o n t ro l
Tr a n s m it R e c e iv e C o llis io n Fo r w a rd in g Unknown Sn iffe r H a lf/Fu ll Duplex Sta tu s
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
M a n c h e s te r EN D E C
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
T x /R x In te r fa c e
Po rt 0
Po rt 1
Po rt 2
Po rt 3
Po rt 4
Po rt 5
Po rt 6
Po rt 7
www.galileoT.com
support@galileoT.com
Tel: +1-408.367.1400
Fax: +1-408.367.1401
GT-48001A Switched Ethernet Controller
Contents
1. Functional Overview .. 6
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 The GalNet Switching Architecture .......... 6 Ethernet Ports ......... 6 Address Recognition .............. 7 CPU Packet Routing .............. 7 Intervention Mode .... 7 Network Management Features ...... 7 DRAM Interface ....... 7 PCI Interface ........... 7
2. Pin Information ........... 8
2.1 2.2 Logic Symbol ........... 8 Pin Functions and Assignment ....... 9
3. Operational Overview ............. 13
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Enabling/Disabling the GT-48001A ........13 Basic Operation .....13 Address Learning ..14 Packet Buffering ....14 Packet Forwarding ......14 The GalNet Protocol .............14 Terminology ...........14
4. MAC Address Learning Process..... 16
4.1 4.2 4.3 4.4 4.5 Address Recognition ............16 Recovery Process ..........16 Address Aging .......17 Static Addresses ...17 Address Recognition Failure .........17
5. GT-48001A Buffers and Queues ..... 18
5.1 Receive Buffer Threshold Programming ......19
6. Packet Forwarding ... 20
6.1 6.2 6.3 Forwarding a Unicast Packet to a Local Port ........20 Forwarding a Unicast Packet to a Port in a Different GalNet Device .....20 Forwarding a Multicast Packet ......21 6.3.1 Local Ports ............ 21 6.3.2 Between GalNet Devices ........ 21 6.3.2.1 CPU Disabled ......... 21 6.3.2.2 CPU Enabled .......... 21 Forwarding a Packet to the CPU Directly .....22 Forwarding a Packet from the CPU to a GalNet Device ...... 24 CRC Generation ....25 Tx Watchdog Timer ..............25
6.4 6.5 6.6 6.7
7. Device Table Operation .......... 26
7.1 7.2 7.3 Automatic Device Table Initialization ............26 Manual Device Table Initialization ..........26 Programming Device Numbers .....26
2
Revision 1.6
GT-48001A Switched Ethernet Controller
8. Unicast Intervention Mode ...... 27
8.1 Unicast Intervention Mode Address Space ........... 28
9. Address Table ........... 29 10. GalNet Messaging Protocol .... 31
10.1 GalNet Protocol Region ....... 31 10.2 GalNet Messages Between Devices ........... 33 10.2.1 NEW_ADDRESS Message between GalNet devices ... 33 10.2.2 BUFFER_REQUEST Message between GalNet devices ...... 34 10.2.3 START_OF_PACKET Message between GalNet devices ..... 34 10.2.4 PACKET_TRANSFER Message between GalNet devices .... 35 10.2.5 END_OF_PACKET Message between GalNet devices ......... 35 10.3 GalNet Messages Between a GalNet Device and a CPU .... 36 10.3.1 NEW_ADDRESS Message (GalNet to CPU) ....... 36 10.3.2 NEW_ADDRESS Message (CPU to GalNet) ....... 37 10.3.3 BUFFER_REQUEST Message (GalNet to CPU) .......... 38 10.3.4 BUFFER_REQUEST Message (CPU to GalNet) .......... 38 10.3.5 START_OF_PACKET Message (GalNet to CPU)......... 39 10.3.6 START_OF_PACKET Message (CPU to GalNet)......... 39 10.3.7 PACKET_TRANSFER Message (GalNet to CPU 16 Block Buffer)....... 40 10.3.8 PACKET_TRANSFER Message (GalNet to CPU in Unicast Intervention Mode).......... 41 10.3.9 PACKET_TRANSFER Message (CPU to GalNet) ........ 41 10.3.10 END_OF_PACKET Message (GalNet to CPU 16 Block Buffer)............ 42 10.3.11 END_OF_PACKET Message (GalNet to CPU in Unicast Intervention Mode) ..... 42 10.3.12 END_OF_PACKET Message (CPU to GalNet) .... 43
11. PCI Bus Operation .... 44
11.1 11.2 11.3 11.4 11.5 11.6 PCI Configuration Header Registers ........... 44 Accessing DRAM and Internal Registers through the PCI Interface ...... 44 PCI Bandwidth/Performance Issues ............ 44 Plug-and-Play Considerations In PCI Systems ..... 45 Unused PCI Bus in Stand-Alone Systems ............ 45 PCI Bus Arbiter in Multiple GalNet Device Systems ...... 45
12. Ethernet Interfaces ... 46
12.1 Media Access Control (MAC) ....... 46 12.2 Illegal Frames ....... 46 12.3 Selecting the Duplex Mode ........... 46 12.3.0.1 Packet Transmission .... 46 12.4 Backoff Algorithm Options ............ 46 12.5 Manchester Encoder/Decoder ...... 46 12.6 Link Integrity and Auto Polarity Detector ..... 47 12.7 Data Blinder .......... 47 12.8 Inter-Packet Gap (IPG) ........ 47 12.9 Partition Mode ....... 47 12.9.1 Enabling Partition Mode ......... 47 12.9.2 Entering Partition State.. 47 12.9.3 Exiting from Partition State ........... 47 12.10 Back-pressure ....... 48 12.11 VLAN Tagging Support ........ 48 12.12 Serial Modes ......... 48 12.12.1 Signal Polarity in Specific Serial Modes ......... 48 12.12.2 10BaseT Mode ..... 48 3
Revision 1.6
|
|
