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Details, datasheet, quote on part number:GT-48006A
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| Part: | GT-48006A |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => Controllers |
| Description: | Low Cost Two Port 10/100 Ethernet Bridge/switch Controller |
| Company: | Marvell Semiconductor, Inc. |
| Datasheet: | Download GT-48006A datasheet File size : 361 kB |
| Request For quote: | Find where to buy GT-48006A
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Datasheet text preview:
GT-48006A
Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller FEATURES
· Single-chip, low-cost, two port 10/100Mbps Ethernet bridge/switch - Provides packet switching functions between two 10/100Mbps, auto-negotiated on-chip Fast Ethernet ports - Ideal for dual speed repeater and 2-port bridge applications · Incorporates two 802.3 compliant 10/100Mbps Media Access Controllers - Direct Interface to MII (Media Independent Interface) - Half/Full Duplex Support (up to 200 Mbps/port) - IEEE 802.3 100Base-TX, T4, and FX compatible - Support for backpressure in half-duplex mode · Auto-negotiation supported through MII Interface - Can be disabled on a per-port basis · High-Performance Switching Engine - Performs forwarding and filtering at full wire speed - 148,800 packets/sec on each Ethernet port
Preliminary Revision 1.2 8/4/98
Please contact Galileo Technology for possible updates before finalizing a design.
· Direct support for packet buffering - Glueless interface to 1or 2Mbyte of 50ns EDO DRAM - Up to 1K buffers, 1536-bytes each - Dynamic or fixed buffer allocation for each port · Supports `Store and Forward' switching approach - Low last-bit in to first-bit out delay - Provides packet buffering in overloaded networks · High visibility LED interface - 3 pin serial LED interface for detailed status information per port · Advanced address recognition - Intelligent address recognition mechanism enables forwarding rate at full wire speed - Self-learning mechanism - Supports up to 16K Unicast addresses and unlimited Multicast/Broadcast addresses · Low-power 0.5u 3.3V process (5V tolerant) · 100 pin PQFP package
EDO DRAM
10 Mbps Segment
GT-48006A
100 Mbps Segment
10/100 Repeater Chip
10/100 Repeater Chip
10/100 Repeater Chip
10/100 Repeater Chip
Four Ports 10/100BaseT
Four Ports 10/100BaseT
Four Ports 10/100BaseT
Four Ports 10/100BaseT
www.galileoT.com
support@galileoT.com
Tel: +1-408.367.1400
Fax: +1-408.367.1401
GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
1.
Functional Overview
The GT-48006A is a high-performance/low-cost, two-port 10/100Mbps Ethernet bridge/switch that provides packet switching/bridging functions between two on-chip 10/100Mbps auto-negotiated ports. The GT-48006A is intended for applications that need to bridge between two 10/100BaseX collision domains, such as: · Autonegotiating "dual speed" 10/100 repeaters · Unmanaged 10/100 bridges · Fiber to 100BaseTX media converters The GT-48006A provides no network management functions (other than LEDs). OEMs requiring management should consider the GT-48002A and GT-48004A 100BaseTX switches, or Galileo's GalaxyTM Family of low-cost desktop switching components (the GT-48212 and GT-48208.)
1.1
Fast Ethernet Ports
The GT-48006A integrates two Fast Ethernet ports each capable of operation at 10/100Mbps (half-duplex) or 20/ 200Mbps (full-duplex). Two Media Independent Interfaces (MII) are provided for glueless connection to off-the-shelf PHY chips. The GT-48006A supports full auto-negotiation for capable PHYs. The speed (10 or 100 Mbps) and duplex (half or full) to which the PHY resolves to operate is automatically reported to the GT-48006A. The port can also be forced to operate in a specific duplex mode, if so desired. Each port includes the Media Access Control function (MAC); the serial LED and MDC/MDIO interface is shared between the ports. The Fast Ethernet ports support backpressure in half-duplex mode. When backpressure is enabled, and there is no receive buffer available for incoming traffic, the GT-48006A will force a JAM pattern on the receiving port.
1.2
Address Recognition
The GT-48006A can recognize up to 16,000 different Unicast MAC addresses and unlimited Multicast/Broadcast MAC addresses. An intelligent address recognition mechanism enables filtering and forwarding packets at full Fast Ethernet wire speed.
1.3
DRAM Interface
GT-48006A interfaces directly to 1Mbyte or 2Mbyte of EDO DRAM. The DRAM is used to store the incoming/outgoing packets as well as the address table and other device data structures. The interface to EDO DRAM is glueless; all signals needed to control EDO devices are provided.
1.4
Packet Buffers
Incoming packets are buffered in the DRAM array. These buffers provide elastic storage for transferring data between low-speed and high-speed segments. The packet buffers are managed automatically by the GT-48006A.
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GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
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2.1
Pin Information
Logic Symbol
GT-48006
DData[31:0] DAddr[8:0] RAS[1:0]* CAS* WE* 2 2 Vtol 2 4 TxEn[1:0] TxClk[1:0] TxD0[3:0] TxD1[3:0] 4 4 2 2 RxD0[3:0] RxD1[3:0] RxEr[1:0] RxClk[1:0] RxDV[1:0] Crs[1:0] Col[1:0] MDC MDIO 32 9
DRAM Interface
MII Interface
4
Rst* Clk LEDData LEDStb LEDClk Scan* TriState* Aging
Miscellaneous Interface
2 2 2
3
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