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Details, datasheet, quote on part number:GT-48208
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| Part: | GT-48208 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => Controllers |
| Description: | Advanced Switched Ethernet Controllers For 10+10/100 Basex |
| Company: | Marvell Semiconductor, Inc. |
| Datasheet: | Download GT-48208 datasheet File size : 1658 kB |
| Request For quote: | Find where to buy GT-48208
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Datasheet text preview:
GT-482xx
Galileo
GT-48212 / GT-48208 / GT-48207
Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Preliminary Revision 1.2 1/27/99
Ple as e contact Galileo Technology for possible u pd ate s before finalizing a design.
FEATURES
· Single-chip Switched Ethernet Controllers for 10 and 10/100Base-X
- Provides packet switching functions between eight or 12 Ethernet ports and two AutoNegotiated on-chip Fast Ethernet ports - Switch expansion via Fast MII port
· D irect support for packet buffering
- 1Mbyte: using one device - 256Kx32-bit Synchronous graphics RAM (SGDRAM) - 4Mbyte: using two devices - 1Mx16bit SDRAM - U p to 2K buffers, 1536-bytes each, dynamically allocated to the receive queues and CPU
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
· Three versions for different cost/performance points
- GT- 48212: 12 10BaseT ports, two 100BaseX ports and advanced management features - GT- 48208: eight 10BaseT ports, two 100BaseX ports and advanced management features - GT- 48207: eight 10BaseT ports, two 100BaseX ports with no management features
· H igh observability LED interface
- Three pin serial LED interface for additional status information per port
· Advanced address recognition on-chip
- Intelligent address recognition mechanism enables forwarding rate at full wire speed - Self-learning mechanism - Supports up to 8K Unicast addresses and unlimited Multicast/Broadcast addresses - M ulticast address support in Address Table - Broadcast storm filtering
· Low-cost 32-bit CPU interface for management
- Glueless interface to IDT 3041, Motorola ColdFire, Intel i960ŪR/Jx CPUs, and GT-641xx controllers. - Simple interface to other 32/64-bit CPUs
· Extensive network management support
- R epeater MIB counters allowing implementation of four RMON groups - H ardware assist for Spanning Tree algorithm - C PU access to Address Table - C PU Query - Ability to read the information from the Address Table - Ability to define static addresses - M onitoring (sniffer) mode
· Management CPU not required
- Allows for cost sensitive unmanaged designs
· Eight or Twelve 802.3 compliant Ethernet ports
- 10Mbps Half-Duplex or 20Mbps Full-Duplex - Serial mode selectable per port: 10Base-T or FL
· Port locking for security · Automatic address aging support · Priority queuing based on MAC address or 802.1Q tag · Port and MAC address based VLAN · IP Multicast support · Flexible software or hardware intervention in packet routing decisions · Packet sampling management technology
· Tw o Fast Ethernet Media Access Controllers
Dir ect Interface to MII Half/Full Duplex Support IEEE 802.3 100Base-TX, T4, and FX compatible Full MII Management Support (MDC/MDIO) Auto-N egotiation supported through MII Interface
· Flow Control on all ports
- Standar d 802.3x flow control for Full Duplex mode - Back pressure for Half Duplex mode
www.galileoT.com
info@galileoT.com
Tel: 408-367-1400
Fax: 408-367-1401
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
- Takes "snapshots" of packets and counters at programmable intervals - A llow s for the implementation of HP-EASE or sampled RMON with low-cost CPUs
· 3.3V with 5V tolerant I/Os · 208 pin PQFP package
· 12 General Purpose Output pins (LEDs, etc.) GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
Block Diagram of Typical Managed Switch (Two 100 Mbit Ports + 12 10 Mbit Ports)
CPU (optional)
C P U Bus (when CPU present)
SDRAM
GT-48212
1 0 B a s e T Filters
100BaseTX PHY/XCVR
1 2 x 10BaseT
2 x 100BaseTX
Block Diagram of Typical Managed Switch (Two 100 Mbit Ports + 24 10 Mbit Ports)
CPU (optional)
C P U Bus (when CPU present)
SDRAM
GT-48212
FAST MII
GT-48212
SDRAM
1 0 B a s e T Filters
100BaseTX PHY/XCVR
1 0 B a s e T Filters
100BaseTX PHY/XCVR
1 2 x 10BaseT
1 x 100BaseTX
1 2 x 10BaseT
1 x 100BaseTX
2
Revision 1.2
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Table of Contents
1. General Description ........... 9
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 Fast Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flow Control and Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Synchronous GRAM/DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IP Multicast and VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Priority Queueing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Network Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Differences Between the GT-48212, GT-48208 and GT-48207 . . . . . . . . . . . . . . . . . . . 12 Pin Functions and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packet Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packet Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 20
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
2. 3.
Pinout ........ 13
2.1 3.1 3.2 3.3 3.4 3.5
Galaxy Family Overview ........... 19
4. 5.
Microarchitectural Overview .... 21 Buffers and Queues ......... 23
5.1 5.2 Rx Buffer Threshold Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Head-of-Line Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Forwarding Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Learning Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locked Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Entry Update and Query from CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Recognition Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forwarding Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forwarding a Unicast Packet to a Local Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forwarding a Multicast Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forwarding a Packet to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forwarding a Packet from the CPU to the GT-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . . Intervention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IG MP Packet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tx Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 28 28 30 31 31 31 33 33 33 34 35 35 35 36
6.
MAC Address Table ......... 26
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10
7.
Packet Forwarding ........... 33
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8
R evision 1.2
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