|
|
Part: DS21Q42
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: Enhanced Quad T1 Framer
Company: Maxim Integrated Products
Datasheet: Download DS21Q42 datasheet File size : 93 kB
Request For quote: Find where to buy DS21Q42
Datasheet text preview:
DS21Q42 Enhanced Quad T1 Framer
www.maxim-ic.com
FEATURES
§ § § § § § § § § § § § Four T1 DS1/ISDN-PRI/J1 framing transceivers All four framers are fully independent Each of the four framers contain dual twoframe elastic-store slip buffers that can connect to asynchronous backplanes up to 8.192MHz 8-bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola) Programmable output clocks for Fractional T1 Fully independent transmit and receive functionality Integral HDLC controller with 64-byte buffers configurable for FDL or DS0 operation Generates and detects in-band loop codes from 1 to 8 bits in length including CSU loop codes Pin compatible with DS21Q44 E1 enhanced quad E1 framer 3.3V supply with 5V tolerant I/O; low-power CMOS Available in 128-pin TQFP package IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive Fram r e Transmt i Form tter a FRAMER #0 FRAMER #1 FRAMER #2 FRAMER #3 Control Port Elastic Store Elastic Store
ACTUAL SIZE
QUAD T1 FRAMER
ORDERING INFORMATION
DS21Q42T DS21Q42TN 0°C to +70°C -40°C to +85°C
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B quad T1 framer. The DS21Q42 contains four framers that are configured and read through a common microprocessor-compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All four framers in the DS21Q42 are totally independent; they do not share a common framing synchronizer. The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (1290), AT&T TR54016, and ITU G.704 and G.706.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata. 1 of 116 062602
DS21Q42
1. INTRODUCTION
The DS21Q42 is a superset version of the popular DS21Q41 quad T1 framer offering the new features listed below. All of the original features of the DS21Q41 have been retained and software created for the original device is transferable to the DS21Q42.
NEW FEATURES
· Additional hardware signaling capability including: Receive signaling re-insertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Interrupt generated on change of signaling data Full HDLC controller with 64-byte buffers in both transmit and receive paths. Configurable for FDL or DS0 access Per-channel code insertion in both transmit and receive paths Ability to monitor one DS0 channel in both the transmit and receive paths RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state Detects AIS-CI 8.192 MHz clock synthesizer Perchannel loopback Ability to calculate and check CRC6 according to the Japanese standard Ability to pass the FBit position through the elastic stores in the 2.048 MHz backplane mode IEEE 1149.1 support
· · · · · · · · · · · · · · · · · · · · · · · · ·
FEATURES
Four T1 DS1/ISDNPRI/J1 framing transceivers All four framers are fully independent Frames to D4, ESF, and SLC96 R formats Each of the four framers contain dual twoframe elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz 8bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola) Extracts and inserts robbed bit signaling Detects and generates yellow (RAI) and blue (AIS) alarms Programmable output clocks for Fractional T1 Fully independent transmit and receive functionality Generates and detects inband loop codes from 1 to 8 bits in length including CSU loop codes Contains ANSI one's density monitor and enforcer Large path and line error counters including BPV, CV, CRC6, and framing bit errors Pin compatible with DS21Q44 E1 Enhanced Quad E1 Framer 3.3V-supply with 5V tolerant I/O; low power CMOS Available in 128pin TQFP package
2 of 116
DS21Q42
FUNCTIONAL DESCRIPTION
The receive side framer locates D4 (SLC96) or ESF multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz. The transmit side of the DS21Q42 is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for T1 transmission.
READER'S NOTE:
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 8bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: D4 SLC96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL Superframe (12 frames per multiframe) Multiframe Structure Subscriber Loop Carrier 96 Channels (SLC96 is an AT&T registered trademark) Extended Superframe (24 frames per multiframe) Multiframe Structure Bipolar with 8 Zero Substitution Cyclical Redundancy Check Terminal Framing Pattern in D4 Signaling Framing Pattern in D4 Framing Pattern in ESF Multiframe Bit Oriented Code High Level Data Link Control Facility Data Link
3 of 116
DS21Q42
Figure 1-1. DS21Q42 ENHANCED QUAD T1 FRAMER
4 of 116
DS21Q42
TABLE OF CONTENTS
1. INTRODUCTION ............2 2. DS21Q42 PIN DESCRIPTION .........8 3. DS21Q42 PIN FUNCTION DESCRIPTION .........15 4. DS21Q42 REGISTER MAP .... 22 5. PARALLEL PORT ......... 26 6. CONTROL, ID, AND TEST REGISTERS....26 7. STATUS AND INFORMATION REGISTERS ........... 37 8. ERROR COUNT REGISTERS........45 9. DS0 MONITORING FUNCTION ......... 48 10. SIGNALING OPERATION ...50 10.1. PROCESSOR-BASED SIGNALING ..... 50 10.2. HARDWARE-BASED SIGNALING ..... 52 11. PERCHANNEL CODE (IDLE) GENERATION AND LOOPBACK ...... 53 11.1. TRANSMIT SIDE CODE GENERATION ...........53 11.1.1. Simple Idle Code Insertion and PerChannel Loopback ....... 54 11.1.2. Per-Channel Code Insertion............55 11.2. RECEIVE SIDE CODE GENERATION ......... 55 11.2.1. Simple Code Insertion ...........55 11.2.2. Per-Channel Code Insertion...........56 12. CLOCK BLOCKING REGISTERS.....57 13. ELASTIC STORES OPERATION ..... 58 13.1. RECEIVE SIDE......58 13.2. TRANSMIT SIDE ..........58 13.3. MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE ......59
5 of 116
Others parts begin by ds
|
|
|
