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Part: DS21Q44TN
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: DS21Q44 Enhanced Quad E1 Framer
Company: Maxim Integrated Products
Datasheet: Download DS21Q44TN datasheet File size : 93 kB
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DS21Q44 Enhanced Quad E1 Framer
www.maxim-ic.com
FEATURES
§ § § § Four E1 (CEPT or PCM-30)/ISDN-PRI framing transceivers All four framers are fully independent; transmit and receive sections of each framer are fully independent Frames to FAS, CAS, CCS, and CRC4 formats Each of the four framers contain dual twoframe elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz 8-bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola) Easy access to Si and Sa bits Extracts and inserts CAS signaling Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E-bits Programmable output clocks for Fractional E1, per channel loopback, H0 and H12 applications Integral HDLC controller with 64-byte buffers configurable for Sa bits or DS0 operation Detects and generates AIS, remote alarm, and remote multiframe alarms Pin compatible with DS21Q42 enhanced quad T1 framer 3.3V supply with 5V tolerant I/O; low-power CMOS Available in 128-pin TQFP package IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive Fram r e Transmt i Form tter a FRAMER #0 FRAMER #1 FRAMER #2 FRAMER #3 Control Port Elastic Store Elastic Store
§ § § § § § § § § § §
ACTUAL SIZE
QUAD E1 FRAMER
ORDERING INFORMATION
DS21Q44T DS21Q44TN 0°C to +70°C -40°C to +85°C
DESCRIPTION
The DS21Q44 E1 is an enhanced version of the DS21Q43 quad E1 framer. The DS21Q44 contains four framers that are configured and read through a common microprocessor-compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All four framers in the DS21Q44 are totally independent; they do not share a common framing synchronizer. The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. The
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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062602
DS21Q44
device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and I.431 as well as ETS 300 011 and ETS 300 233.
1. INTRODUCTION
The DS21Q44 is a superset version of the popular DS21Q43 quad E1 framer offering the new features listed below. All of the original features of the DS21Q43 have been retained and software created for the original device is transferable to the DS21Q44.
NEW FEATURES
§ Additional hardware signaling capability including: receive signaling reinsertion to a backplane multiframe sync availability of signaling in a separate PCM data stream signaling freezing interrupt generated on change of signaling data Perchannel code insertion in both transmit and receive paths Full HDLC controller with 64-byte buffers in both transmit and receive paths. Configurable for Sa bits or DS0 access RCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state 8.192MHz clock synthesizer Ability to monitor one DS0 channel in both the transmit and receive paths Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233 Automatic RAI generation to ETS 300 011 specifications IEEE 1149.1 support
§ § § § § § § §
FUNCTIONAL DESCRIPTION
The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz. The transmit side in each framer is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for E1 transmission.
READER'S NOTE:
This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us frame, there are 32 8bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: FAS CAS MF Si Frame Alignment Signal Channel Associated Signaling Multiframe International bits
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CRC4 CCS Sa E-bit
Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error Bits
DS21Q44
Figure 1-1. DS21Q44 ENHANCED QUAD E1 FRAMER
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DS21Q44
TABLE OF CONTENTS
1. INTRODUCTION ............2 2. DS21Q44 PIN DESCRIPTION .........7 3. DS21Q44 PIN FUNCTION DESCRIPTION .........13 4. DS21Q44 REGISTER MAP .... 20 5. PARALLEL PORT ......... 24 6. CONTROL, ID, AND TEST REGISTERS....24 7. STATUS AND INFORMATION REGISTERS ........... 35 8. ERROR COUNT REGISTERS........41 9. DS0 MONITORING FUNCTION ......... 44 10. SIGNALING OPERATION ...46 10.1 PROCESSOR-BASED SIGNALING ....... 46 10.2 HARDWARE-BASED SIGNALING ....... 49 11. PERCHANNEL CODE GENERATION AND LOOPBACK ....50 11.1 TRANSMIT SIDE CODE GENERATION ....... 50 11.1.1 Simple Idle Code Insertion and Per-Channel Loopback.........50 11.1.2 Per-Channel Code Insertion....51 11.2 RECEIVE SIDE CODE GENERATION..52 12. CLOCK BLOCKING REGISTERS......53 13. ELASTIC STORES OPERATION .......54 13.1 RECEIVE SIDE........55 13.2 TRANSMIT SIDE .... 55 14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .... 55 14.1 HARDWARE SCHEME ... 55 14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME.....56 14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME........58
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DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0 ......... 60 15.1 15.2 15.3 15.4 GENERAL OVERVIEW .. 60 HDLC STATUS REGISTERS ......... 61 BASIC OPERATION DETAILS ..... 62 HDLC REGISTER DESCRIPTION ......... 63
16. INTERLEAVED PCM BUS OPERATION...70 17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...73 17.1 17.2 17.3 17.4 DESCRIPTION ........ 73 TAP CONTROLLER STATE MACHINE ........ 74 INSTRUCTION REGISTER AND INSTRUCTIONS ..... 76 TEST REGISTERS ........... 78
18. TIMING DIAGRAMS.....82 19. OPERATING PARAMETERS .............92 20. 128-PIN TQFP PACKAGE SPECIFICATIONS ......105
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