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Part: DS21Q50L
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: DS21Q50 Quad E1 Transceiver
Company: Maxim Integrated Products
Datasheet: Download DS21Q50L datasheet File size : 93 kB
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DS21Q50 Quad E1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 22AWG (0.6mm) twisted-pair cables from 0km to over 2km in length. The device can generate the necessary G.703 waveshapes for both 75 coax and 120 twisted-pair cables. The on-board jitter attenuators (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framers locate the frame and multiframe boundaries and monitor the data streams for alarms. The device contains a set of internal registers, from which the user can access and control the operation of the unit by the parallel control port or serial port. The device fully meets all of the latest E1 specifications including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431 ETS 300 011, ETS 300 233, and ETS 300 166 as well as CTR12 and CTR4.
FEATURES
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§ § § § § § § § § § § § § § Four Complete E1 (CEPT) PCM-30/ISDN-PRI Transceivers Long-Haul and Short-Haul Line Interfaces 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Frames to FAS, CAS, CCS, and CRC4 Formats 4MHz/8MHz/16MHz Clock Synthesizer Flexible System Clock with Automatic Source Switching on Loss-of-Clock Source Two-Frame Elastic-Store Slip Buffer on the Receive Side Interleaving PCM Bus Operation Up to 16.384MHz Configurable Parallel and Serial Port Operation Detects and Generates Remote and AIS Alarms Fully Independent Transmit and Receive Functionality Four Separate Loopback Functions PRBS Generation/Detection/Error Counting 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits Eight Additional User-Configurable Output Pins 100-Pin LQFP Package (14mm)
APPLICATIONS
DSLAMs Routers IMA and WAN Equipment §
§
PIN CONFIGURATION ORDERING INFORMATION
PART DS21Q50L DS21Q50LN TEMP RANGE 0°C to +70°C -40°C to +85°C PIN-PACKAGE 100 LQFP (14mm) 100 LQFP (14mm)
TOP VIEW
DS21Q50
10 0 1
LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS21Q50
TABLE OF CONTENTS
1. 2. INTRODUCTION .............6 PIN DESCRIPTION..........9 2.1
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7
PIN FUNCTION DESCRIPTION.........15
System (Backplane) Interface Pins .............15 Alternate Jitter Attenuator ...........16 Clock Synthesizer..........16 Parallel Port Control Pins...........16 Serial Port Control Pins .....17 Line Interface Pins..............18 Supply Pins ..........18
3.
HOST INTERFACE PORT.....20 3.1 3.2 3.3 PARALLEL PORT OPERATION ........20 SERIAL PORT OPERATION ....20 REGISTER MAP ...........23 POWER-UP SEQUENCE .........25 FRAMER LOOPBACK ............28 AUTOMATIC ALARM GENERATION .....29 REMOTE LOOPBACK ............30 LOCAL LOOPBACK......30 CRC4 SYNC COUNTER ........34 BPV OR CODE VIOLATION COUNTER ..........39 CRC4 ERROR COUNTER ......40 E-BIT/PRBS BIT ERROR COUNTER ....40 FAS ERROR COUNTER.........41
4.
CONTROL, ID, AND TEST REGISTERS....24 4.1 4.2 4.3 4.4 4.5
5. 6.
STATUS AND INFORMATION REGISTERS ...........32 5.1 6.1 6.2 6.3 6.4 ERROR COUNT REGISTERS........39
7. 8. 9. 10. 11.
DS0 MONITORING FUNCTION .........42 PRBS GENERATION AND DETECTION ...45 SYSTEM CLOCK INTERFACE...........46 TRANSMIT CLOCK SOURCE ........47 IDLE CODE INSERTION...48
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DS21Q50
12. 13. 14. 15. 16. 16.1 16.2 16.3 17. 18. 19. 19.1 19.2 20. 21. 21.1 21.2 21.3 21.4 21.5 21.6 22.
PER-CHANNEL LOOPBACK ..........49 ELASTIC STORE OPERATION ......49 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION ..........50 USER-CONFIGURABLE OUTPUTS........53 LINE INTERFACE UNIT ...56 RECEIVE CLOCK AND DATA RECOVERY ......56 TRANSMIT WAVESHAPING AND LINE DRIVING ...........57 JITTER ATTENUATORS .........60 CMI (CODE MARK INVERSION)............62 INTERLEAVED PCM BUS OPERATION........64 FUNCTIONAL TIMING DIAGRAMS......66 RECEIVE TIMING DIAGRAMS ........66 TRANSMIT TIMING DIAGRAMS............68 OPERATING PARAMETERS ..........72 AC TIMING PARAMETERS AND DIAGRAMS ............73 MULTIPLEXED BUS AC CHARACTERISTICS ..........73 NONMULTIPLEXED BUS AC CHARACTERISTICS .........76 SERIAL PORT ..............79 RECEIVE AC CHARACTERISTICS.........80 TRANSMIT AC CHARACTERISTICS ......82 SPECIAL MODES AC CHARACTERISTICS......84 PACKAGE DRAWING .......85
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DS21Q50
LIST OF FIGURES
Figure 1-1. Block Diagram ..........8 Figure 3-1. Serial Port Operation Mode 1 .........21 Figure 3-2. Serial Port Operation Mode 2 .........21 Figure 3-3. Serial Port Operation Mode 3 .........22 Figure 3-4. Serial Port Operation Mode 4 .........22 Figure 16-1. External Analog Connections (Basic Configuration) ....58 Figure 16-2. External Analog Connections (Protected Interface) ......58 Figure 16-3. Transmit Waveform Template......59 Figure 16-4. Jitter Tolerance......61 Figure 16-5. Jitter Attenuation............61 Figure 17-1. CMI Coding ..........62 Figure 17-2. CMI Code Violation Example ......63 Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) ....65 Figure 19-1. Receive Frame and Multiframe Timing..........66 Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)......66 Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) .......67 Figure 19-4. Receive Interleave Bus Operation .........67 Figure 19-5. Transmit Frame and Multiframe Timing ........68 Figure 19-6. Transmit Boundary Timing...........68 Figure 19-7. Transmit Interleave Bus Operation........69 Figure 19-8. Framer Synchronization Flowchart........70 Figure 19-9. Transmit Data Flow .......71 Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) ..........74 Figure 21-2. Intel Bus Write Timing (PBTS = 0).......74 Figure 21-3. Motorola Bus AC Timing (PBTS = 1)...75 Figure 21-4. Intel Bus Read Timing (PBTS = 0)........77 Figure 21-5. Intel Bus Write Timing (PBTS = 0).......77 Figure 21-6. Motorola Bus Read Timing (PBTS = 1) .........78 Figure 21-7. Motorola Bus Write Timing (PBTS = 1) ........78 Figure 21-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ......79 Figure 21-9. Receive AC Timing (Receive Elastic Store Disabled) ..80 Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled) ..........81 Figure 21-11. Transmit AC Timing (IBO Disabled) ..83 Figure 21-12. Transmit AC Timing (IBO Enabled) ...83 Figure 21-13. NRZ Input AC Timing..........84
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LIST OF TABLES
Table 2-A. Pin Assignments (by Function) .........9 Table 2-B. Pin Assignment (by LQFP Pin Number)..12 Table 3-A. Bus Mode Select......20 Table 3-B. Register Map............23 Table 4-A. Sync/Resync Criteria........26 Table 5-A. Alarm Criteria..........34 Table 8-A. Transmit PRBS Mode Select...........45 Table 8-B. Receive PRBS Mode Select ............45 Table 9-A. Master Port Selection .......47 Table 9-B. Synthesizer Output Select..........47 Table 15-A. OUTA and OUTB Function Select ........55 Table 16-A. Line Build-Out Select in LICR .....57 Table 16-B. Transformer Specifications............57 Table 18-A. IBO Device Assignment..........64 Table 18-B. IBO System Clock Select ........65
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