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Part: DS21Q55
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: DS21Q55 Quad T1/E1/J1 Transceiver Preliminary
Company: Maxim Integrated Products
Datasheet: Download DS21Q55 datasheet File size : 93 kB
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PRODUCT PREVIEW X
Product Preview
DS21Q55
DS21Q55 Quad T1/E1/J1 Transceiver
FEATURES:
Complete T1 (DS1)/ISDNPRI/J1 transceiver functionality § Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality § Short- and long-haul line interface for clock/data recovery and wave shaping § CMI coder/decoder § Crystal- less jitter attenuator § Dual HDLC controllers § On-chip programmable BERT generator and detector § Internal software-selectable receive and transmit side termination resistors § Dual two- frame elastic-store slip buffers to interface backplanes up to 16.384MHz § 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered network clock § Programmable output clocks for fractional T1, E1, H0, and H12 applications § Interleaving PCM bus operation § 8-bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola § IEEE 1149.1 JTAG-boundary scan § 3.3V supply with 5V tolerant I/O § Signaling System 7 (SS7) support
APPLICATIONS:
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Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment DSL Add/Drop Multiplexers
ORDERING INFORMATION
DS21Q55 DS21Q55N 27mm BGA (0°C to +70°C) 27mm BGA (-40°C to +85°C)
1. DESCRIPTION
The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family of products. www.maxim-ic.com Note: This Product Preview contains preliminary information and is subject to change without notice. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm. Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview
DS21Q55
1. DESCRIPTION
The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family of products. The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary wave shapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 wave shapes for both 75O coax and 120O twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal- less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to optical networks. On the transmit side, clock data and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane interface section. Each transceiver has two HDLC controllers. The HDLC controllers transmit and receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has a 128-byte transmit FIFO and a 128-byte receive FIFO, thus reducing the amount of processor overhead required to manage the flow of data. In addition, there is built- in support for reducing the processor time required to handle SS7 applications. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (two DS21Q55s) to share a high-speed backplane. The parallel port provides access for control and configuration of all the DS21Q55's features. The Extended System Information Bus (ESIB) function allows up to eight transceivers, 2 DS21Q55s, to be accessed via a single read for interrupt status or other user selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.
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Product Preview
DS21Q55
The device fully meets all of the latest E1 and T1 specifications, including the following: § § § § § ANSI: AT&T: ITU: ETSI: Japanese: T1.403-1995, T1.231-1993, T1.408 TR54016, TR62411 G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161 ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12 JTG.703, JTI.431, JJ-20.11 (CMI coding only)
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DS21Q55
1.1 FEATURE HIGHLIGHTS
The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor's T1 and E1 transceivers plus many new features.
1.1.1 General
§ § § § § § § 27mm, 1.27 pitch BGA 3.3V supply with 5V tolerant inputs and output s Pin compatible with DS21x5y family Software compatible with the DS2155 Evaluation kits IEEE 1149.1 JTAG-boundary scan Driver source code available from the factory
1.1.2 Line Interface
§ § § § § § § § § § § § § § § § § § § § § § Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.276MHz, or 12.552MHz for T1-only operation Fully software configurable Short- and long-haul applications Automatic receive sensitivity adjustments Ranges include 0dB to -43dB or 0dB to -15dB for E1 applications; 0dB to -36dB or 0dB to -15dB for T1 applications Receive level indication in 2.5dB steps from -42.5dB to -2.5dB Internal receive termination option for 75O, 100O, and 120O lines Monitor application gain settings of 20dB, 26dB, and 32dB G.703 receive-synchronization signal- mode Flexible transmit-waveform generation T1 DSX-1 line build-outs T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75O coax and 120O twisted cables AIS generation independent of loopbacks Alternating ones and zeros generation Square-wave output Open-drain output option NRZ format option Transmitter power-down Transmitter 50mA short-circuit limiter with exceeded indication of current limit Transmit open-circuit-detected indication Line interface function can be completely decoupled from the framer/formatter
1.1.3 Clock Synthesizer
§ § Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from recovered receive clock
1.1.4 Jitter Attenuator
§ 32-bit or 128-bit crystal- less jitter attenuator
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DS21Q55
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Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication
1.1.5 Framer/Formatter
§ § § § § Fully independent transmit and receive functionality Full receive- and transmit-path transparency T1 framing formats include D4 (SLC-96) and ESF Detailed alarm- and status-reporting with optional interrupt support Large path- and line-error counters for: - T1 BPV, CV, CRC6, and framing bit errors - E1 BPV, CV, CRC4, E-bit, and frame alignment errors - Timed or manual update modes DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths - User-defined - Digital milliwatt ANSI T1.403-1998 support E1ETS 300 011 RAI generation G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-band repeating-pattern generators and detectors - Three independent generators and detectors - Patterns from 1 bit to 8 bits or 16 bits in length RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state Flexible signaling support - Software- or hardware-based - Interrupt generated on change of signaling data - Receive-signaling freeze on loss of sync, carrier loss, or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI generation to ETS 300 011 specifications Expanded access to Sa and Si bits Option to extend carrier- loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support - Ability to calculate and check CRC6 according to the Japanese standard - Ability to generate yellow alarm according to the Japanese standard
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1.1.6 System Interface
§ Dual two- frame, independent receive and transmit elastic stores - Independent control and clocking - Controlled-slip capability with status - Minimum-delay mode supported Maximum 16.384MHz backplane burst rate Supports T1 to CEPT (E1) conversion Programmable output clocks for fractional T1, E1, H0, and H12 applicatio ns Interleaving PCM bus operation
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