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Part: DS3120
Category:
Description:
Company: Maxim Integrated Products
Datasheet: Download DS3120 datasheet File size : 570 kB
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DS3120 28 Channel T1 Framer
www.dalsemi.com
FEATURES
§ § § § § § § § § § § § § § § § § 28 T1 DS1/ISDNPRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing and external timing Supports H.100 / MVIP 8 MHz backplanes Frames to D4, ESF, and SLC-96â Transparent framing mode Frame bit clock gapping option Hardware based signaling option Fully independent transmit and receive functionality Integral HDLC controller with 64-byte buffers; configurable for FDL or DS0 operation Generates and detects inband loop codes from 1 to 8 bits in length DS0 monitor capability Per DS0 channel loopback Software compatible with other Dallas Semiconductor T1 framers 1.8V core supply with 5V tolerant I/O; low power .18 um CMOS 27 mm x 27 mm, 316 lead 1.27 mm pitch PBGA package IEEE 1149.1 support
FUNCTIONAL DIAGRAM
data clock Receive Framer Transmit Formatter 28 T1 Framers data frame sync clock frame sync data
data
Parallel Control Port
DS3120 - (00 C to 700 C) DS3120N - (-400 C to +850 C)
ORDERING INFORMATION
DESCRIPTION
The DS3120 is a highly dense version of Dallas Semiconductor's popular T1 framer series. It shares the same register structure as the DS2151, DS2152, DS21352, DS21552, DS21Q352, DS21Q552, DS2141A, DS21Q41B, DS21Q42, DS21FT42, and DS21FF42. The DS3120 contains 28 fully independent framers that are configured and read through a common microprocessor compatible parallel port. The device meets all of the latest T1 specifications including ANSI T1.4031999, ANSI T1.2311993, AT& T TR 62411 (1290), AT& T TR54016, and ITU G.704 and G.706.
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053001
DS3120
1. INTRODUCTION
The DS3120 is a highly dense version of the popular Dallas Semiconductor T1 framers. Since the DS3120 is primarily intended for use in channelized T3 applications, several features found in other Dallas Semiconductor T1 framers are not included in this device. These features are listed in Table 1-1 below. A list of the main features in the DS3120 is detailed in Table 1-2.
Features Not Included in DS3120 Table 1-1
· · · · No bipolar interface No receive side signaling re-insertion function Limited elastic store functionality Missing signals include RCHBLK, TCHBLK, RCHCLK, TCHCLK, TLINK, TLCLK, RLINK, RLCLK, RMSYNC, RFSYNC, RLOS/LOTC, and FMS
DS3120 Main Features List Table 1-2
· · · · · · · · · · · · · · · · · · · · · · 28 T1 DS1/ISDNPRI/J1 framing transceivers All 28 framers are fully independent Frames to D4, ESF, and SLC96 formats Framing transparent mode Can operate in both loop timing and external timing (common transmit clock) configurations Framing bit clock gapping mode supported Supports H.100 / MVIP 8 MHz interfaces 8bit parallel control port supports both multiplexed and nonmultiplexed buses (Intel or Motorola) Extracts and inserts robbed bit signaling via either software (processor based) or hardware signals Signaling freezing Interrupt generated on change of signaling data Detects and generates yellow (RAI) and blue (AIS) alarms Detects carrier loss (RCL), AIS-CI, and loss of sync (RLOS) Fully independent transmit and receive functionality Generates and detects inband loop codes from 1 to 8 bits in length including CSU loop codes Contains ANSI one's density monitor and enforcer Large path and line error counters including EXZ, CRC6, and framing bit errors HDLC controller with 64byte buffers in both transmit and receive paths; configurable for FDL or DS0 access Perchannel code insertion in both transmit and receive paths Ability to monitor one DS0 channel in both the transmit and receive paths 1.544 MHz to 8.192 MHz clock synthesizer Per channel loopback
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· · · ·
Ability to calculate and check CRC6 according to the Japanese standard Ability to pass the FBit position through the elastic stores in the H.100 / MVIP 8 MHz backplane mode IEEE 1149.1 support 1.8V and 3.3V supply with 5V tolerant I/O; low power CMOS
Reader's Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 8bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: D4 SLC96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL Superframe (12 frames per multiframe) Multiframe Structure Subscriber Loop Carrier 96 Channels (SLC96 is an AT&T registered trademark) Extended Superframe (24 frames per multiframe) Multiframe Structure Bipolar with 8 Zero Substitution Cyclical Redundancy Check Terminal Framing Pattern in D4 Signaling Framing Pattern in D4 Framing Pattern in ESF Multiframe Bit Oriented Code High Level Data Link Control Facility Data Link
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DS3120 28 CHANNEL T1 FRAMER Figure 1-1
28 T1 Framers
Receive Framer Synchronizer Alarm Detection Loop Code Detector CRC/Frame Error Counters One 's Density Monitor S/W Signaling Extraction DS0 Channel Marking DS0 Channel Code Insert DS0 Monitor Receive HDLC & BOM Controller 4
MODE0 to MODE3
RCLK[n]
cloc k sync da ta Payload Loopback
cloc k sync da ta
RNRZ[n] Remote Loopback Framer Loopback
da ta
Force High
8M bps Interleaved Bus Ope ration (IBO) Buffer
cloc k sync RSYNC[n] RSER[n]
Hardware Signaling Extraction sync & clock control cloc k sync 8M bps Interleaved Bus Ope ration (IBO) Buffer cloc k sync Hardware Signaling Inse rtion
Mode Mux
Transmit Formatter AIS Generation DS0 Monitor One 's Density Enforcer Yellow Alarm Generation CRC Generation F-Bit Insertion FDL Insertion Clear Channel Bit 7 Insert S/W Signaling Insertion DS0 Channel Loopback Loop Code Generation DS0 Channel Code Insert DS0 HDLC Insert LOTC mux
cloc k sync da ta
TCLK[n] / RSIG[n] TSYNC[n] / TSIG[n] TSER[n]
TNRZ[n]
Force High
Transmit HDLC & BOM Controller 8M SYNC D0 to D7 / AD0 to AD7 INT* MUX A0 to A5, A7 ALE(AS) / A6 RD*(DS*) WR*(R/W*) BTS 7 8M CLKI 8 CTSYNC CTCLK 8M CLKO CLKSI TEST FIACT* JTCLK JTRST* JTMS JTDI JTDO
1.544MHz to 8.192MHz Synthesizer Parallel Control Port (routed to all blocks) JTAG & Output Control
I/O Supply
FS0 to FS4 C S* 5
8 8
VDD_IO VSS_IO VDD_CORE VSS_CORE
Core Supply
8 8
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TABLE OF CONTENTS
1. INTRODUCTION .............. 2 2. DS3120 SIGNAL DESCRIPTION............. 7 3. DEVICE OPERATING MODES............. 22 4. DS3120 REGISTER MAP ........ 28 5. PARALLEL PORT........... 32 6. CONTROL, ID AND TEST REGISTERS........ 33 7. STATUS AND INFORMATION REGISTERS ........ 44 8. ERROR COUNT REGISTERS.......... 53 9. DS0 MONITORING FUNCTION ........... 56 10. SIGNALING OPERATION... 58
10.1 PROCESSOR BASED SIGNALING......... 59 10.2 HARDWARE BASED SIGNALING......... 60 11. PERCHANNEL CODE (IDLE) GENERATION AND LOOPBACK ........ 61 11.1 TRANSMIT SIDE CODE GENERATION......... 62 11.1.1 Simple Idle Code Insertion and PerChannel Loopback ...... 62 11.1.2 PerChannel Code Insertion ....... 63 11.2 RECEIVE SIDE CODE GENERATION ... 64 11.2.1 Simple Code Insertion.. 64 11.2.2 PerChannel Code Insertion ....... 64 12. DS0 SELECT CONTROL REGISTERS....... 65 12.1 RCHBLK AND TCHBLK USED FOR SIGNALING CONTROL ......... 67 12.2 RCHBLK AND TCHBLK USED FOR HDLC CONTROL ....... 67 13. 14. ELASTIC STORE OPERATION ......... 67 HDLC CONTROLLER.......... 68 GENERAL OVERVIEW........... 68 STATUS REGISTER FOR THE HDLC ..... 69 BASIC OPERATION DETAILS .......... 70 HDLC/BOC REGISTER DESCRIPTION.......... 71
14.1 14.2 14.3 14.4
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