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Part: DS3134
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: Chateau - Channelized T1 And E1 And Universal HDLC Controller
Company: Maxim Integrated Products
Datasheet: Download DS3134 datasheet File size : 570 kB
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Datasheet text preview:
DS3134 Chateau Channelized T1 And E1 And HDLC Controller
www.dalsemi.com
PRELIMINARY
FEATURES
· · · · · · · · · · 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines 256 Independent bi-directional HDLC channels 16 physical ports (16 Tx & 16 Rx) that can be configured as either channelized or unchannelized Two fast (52 Mbps) ports/other ports capable of speeds up to 10 Mbps (unchannelized) Channelized Ports 0 to 15 handle one, two or four T1 or E1 lines Supports up to 64 T1 or E1 data streams Per channel DS0 loopbacks in both direction Support transparent Mode V.54 loopback code detector Onboard Bit Error Rate Tester (BERT) with auto error insertion capability · · · · · · · · · · · · BERT function can be assigned to any HDLC channel or any port 104 Mbps full duplex throughput Large 16 kbits FIFO in both receive and transmit directions Efficient scatter / gather DMA Receive data packets are Time stamped Transmit packet priority setting Local bus allows for PCI bridging or local access Intel or Motorola bus signals supported 25 MHz to 33 MHz 32-bit PCI (V2.1) backplane interface 3.3V low power CMOS with 5V tolerant I/O JTAG support IEEE 1149.1 256 Lead Plastic BGA (27 mm x 27 mm)
DESCRIPTION
The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16 physical ports can handle one, two or four T1 or E1 data streams. The Chateau consists of the following blocks: · Layer Block · HDLC Block · FIFO Block · DMA Block · PCI Bus · Local Bus
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DS3134 There are 16 HDLC Engines (one for each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to 10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0 and 1 and they are capable of operating at speeds up to 52 Mbps. Applications/Markets include: · · · · · · · · · · Channelized T1/E1 Clear channel (unchannelized) T1/E1 Channelized T3/E3 Dual clear channel (unchannelized) T3/E3 High density Frame Relay access xDSL (each port can support up to 10 Mbps) Dual HSSI V.35 SONET/SDH EOC/ECC Termination Any applications require large number of HDLC channels
The device fully meets the following specifications: ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 and PCI Local Bus Specification V2.1 June 1, 1995. ITU Q.921 March 1993 and ISO Standard 3309-1979 Data Communications HDLC Procedures Frame Structure.
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DS3134
REVISION HISTORY
Version 1 (1/30/98) Original release. Version 2 (4/4/98) 1. Assigned signals to leads (Section 2.1). 2. Added more information to Sections 1, 5, 7, and 10. 3. Removed the P3VEN signal pin (Section 2.1 and 2.5). 4. Added FIFO Priority Control bits to the MC register (Section 4.2). 5. Added Abort and Bit Stuffing Control bits to the RHCD and THCD registers (Section 6.2). 6. Changed the Absolute Maximum Voltage Rating and IOH numbers (Section 12). 7. Changed the Low Water Mark definition (Section 7.1). 8. Added Section 14 on Applications. Version 3 (6/22/98) 1. Corrected JTRST* lead from V19 to U19 (Section 2.1). 2. Added TEST lead at C3 (Section 2.1). 3. Added the Valid Receive Done Queue Descriptor bit (Section 8.1.4). 4. Corrected JTAG Device Code from 0000614Ch to 00006143h (Section 11.3). 5. Changed the order of the TABTE & TZSD bits in the THCD Register (Section 6.2). 6. Added JTAG Scan Control Information into Table 11.4A (Section 11.4). 7. Added Minimum Grant & Maximum Latency Settings to PINTL0 (Section 9.2). 8. Remove the HDLC channel restriction that required channels 1 to 128 to be assigned to ports 0 to 7 and HDLC channels 129 to 256 to be assigned to port 8 to 15 (Sections 1, 5.1, 5.3 and 6.1). Version 4 (11/18/98) 1. Added information about queues full and empty states (Sections 8.1.3, 8.1.4, 8.2.3, and 8.2.4). 2. Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive (Section 5.6). 3. Changed BERT Bit and Error Counters to count during loss of receive synchronization (Section 5.6). 4. Corrected Table 1E (Section 1). 5. Added bit numbers to register descriptions. 6. Changed Local Bus Configuration Mode AC Timing Parameter A7 from 5ns to 40ns. (Section 12). Version 5 (09/01/99) 1. Typos corrections and add clarifications.(Section 2.5, 3.5, 4.4, 5.3, 5.5, 5.6, 6.2, 7.1, 8.1.1, 8.2.3) 2. Change the number of T1/E1 support from 64 to 56 due to design over sight (Section 1) 3. Added clarifications for Receive High Water Mark and corrected Transmit Low Water Mark to a value from 1 to smaller or equal to N 2, where N = the number of linked blocks. 4. Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to section 8.1.3 (page 90) 5. Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK #1. 6. Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC #1.
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DS3134 Version 6 (05/01/00) Rev B1/B2 silicon release 1. Typo correction on the following pages: 7, 53, 61, 80, 107, 114 and 115 2. Add (notes) clarifications on the following pages: 60, 63, 73, 76, 87, 88, 90, 93, 95, 110, 111 and 117 3. Update Layer 1 configuration restrictions for silicon Rev B1/B2 release, on page 10. 4. Update reset wait cycles on page 11. 5. Remove bit 1 form register RDMAQ on page 97. 6. Local Bus timing update, corrected t3 and t6 on page 169. 7. Change the number of T1/E1 support from 56 back to 64 (Section 1), this will be supported in the next rev of silicon. 8. Added a product preview page. Version 7 (09/15/00) 1. Update figure 9.1C. 2. Update figure 14C in Section 14. 3. Typo correction.
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TABLE OF CONTENTS
Section 1: Introduction........7 Section 2: Signal Description...... 2.1 Overview / Signal Lead List......... 2.2 Serial Port Interface Signal Description... 2.3 Local Bus Signal Description....... 2.4 JTAG Signal Description...... 2.5 PCI Bus Signal Description......... 2.6 Supply & Test Signal Description........... 16 16 22 24 27 28 31
Section 3: Memory Map............ 32 3.0 Introduction..... 32 3.1 General Configuration Registers........... 32 3.2 Receive Port Registers........ 33 3.3 Transmit Port Registers....... 33 3.4 Channelized Port Registers........ 34 3.5 HDLC Registers....... 35 3.6 BERT Registers........ 35 3.7 Receive DMA Registers....... 35 3.8 Transmit DMA Registers...... 36 3.9 FIFO Registers......... 36 3.10 PCI Configuration Registers for Function 0.... 36 3.11 PCI Configuration Registers for Function 1.... 37 Section 4: General Device Configuration & Status/Interrupt........ 4.1 Master Reset & ID Register Description.......... 4.2 Master Configuration Register Description....... 4.3 Status & Interrupt...... 4.3.1 Status & Interrupt General Description............ 4.3.2 Status & Interrupt Register Description............ 4.4 Test Register Description........... 37 37 38 40 40 43 50
Section 5: Layer One...... 51 5.1 General Description... 51 5.2 Port Register Description........... 55 5.3 Layer One Configuration Register Description........ 59 5.4 Receive V.54 Detector........ 65 5.5 BERT............69 5.6 BERT Register Description........ 70 Section 6: HDLC............ 77 6.1 General Description.. 77 6.2 HDLC Register Description....... 79
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