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Part: DS3143
Category:
Communication
-> Network
-> T/E Carrier and Packetized Products
Description: DS3141/DS3142/DS3143/DS3144 Single/dual/triple/quad DS3/E3 Framers
Company: Maxim Integrated Products
Datasheet: Download DS3143 datasheet File size : 570 kB
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Datasheet text preview:
DESIGN KIT AVAILABLE
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3141, DS3142, DS3143, and DS3144 (DS314x) devices include all necessary circuitry to frame and format up to four separate DS3 or E3 channels. Each framer in these devices is independently configurable to support M23 DS3, C-Bit Parity DS3, or G.751 E3. The framers interface to a variety of line interface units (LIUs), microprocessor buses, and other system components without glue logic. Each DS3/E3 framer has its own HDLC controller, FEAC controller, and BERT, as well as full support for error detection and generation, performance monitoring, and loopbacks.
FEATURES
§ § § § § § § § § § § § § § § § §
One/Two/Three/Four Independent DS3/E3 Framers on a Single Die Framing and Formatting to M23 DS3, C-Bit Parity DS3, and G.751 E3 LIU Interface can be Binary (NRZ) or Dual-Rail (POS/NEG) B3ZS/HDB3 Encoder and Decoder Generate and Detect DS3/E3 Alarms Integrated HDLC Controller for Each Channel Integrated FEAC Controller for Each Channel Integrated Bit Error-Rate Tester (BERT) for Each Channel Large Performance-Monitoring Counters Line, Diagnostic, and Payload Loopbacks Externally Controlled Transmit Overhead Insertion Port Support External Timing or Loop-Timing Framers can be Powered Down When Not Used 8-Bit Processor Port Supports Muxed or Nonmuxed Bus Operation (Intel or Motorola) 3.3V Supply with 5V Tolerant I/O 144-Pin, 13mm x 13mm CSBGA Package IEEE 1149.1 JTAG Support
APPLICATIONS
SONET/SDH Muxes PDH Muxes Digital Cross-Connect Systems Access Concentrators ATM and Frame Relay Equipment Routers
FUNCTIONAL DIAGRAM
LIU INTERFACE POS/NRZ NEG CLK POS/NRZ NEG/LCV CLK EACH FRAMER SYSTEM INTERFACE CLK DATA SYNC OVERHEAD CLK DATA SYNC Dallas Semiconductor DS314x
TRANSMIT FORMATTER RECEIVE FRAMER
ORDERING INFORMATION
PART DS3141 DS3141N DS3142 DS3142 DS3143 DS3143N DS3144 DS3144N NO. OF FRAMERS 1 1 2 2 3 3 4 4 TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 144 CSBGA 144 CSBGA 144 CSBGA 144 CSBGA 144 CSBGA 144 CSBGA 144 CSBGA 144 CSBGA
Pin Configurations appear at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 012003
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
TABLE OF CONTENTS
1. 2. 3. 4. 5. BLOCK DIAGRAM ........ 6 APPLICATION EXAMPLE ..... 6 MAIN FEATURES ......... 7 STANDARDS COMPLIANCE ......... 8 PIN DESCRIPTION ....... 9 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. 7. 6.1 7.1 7.2 TRANSMIT FORMATTER LIU INTERFACE PINS ......... 9 RECEIVE FRAMER LIU INTERFACE PINS........ 9 TRANSMIT FORMATTER SYSTEM INTERFACE PINS ...... 10 RECEIVE FRAMER SYSTEM INTERFACE PINS ........ 12 CPU BUS INTERFACE PINS ......... 14 JTAG INTERFACE PINS...... 14 SUPPLY, TEST, AND RESET PINS....... 14 STATUS REGISTER DESCRIPTION ...... 17 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 TRANSMITTER LOGIC ......... 18
Transmit Clock .... 18 Loss-of-Clock Detection ..... 19
REGISTERS.......... 15 FUNCTIONAL DESCRIPTION ............ 18
7.2.1 7.2.2
7.3 7.4 7.5
RECEIVER LOGIC...... 19 ERROR INSERTION.... 20 LOOPBACKS ............. 20
Line Loopback..... 20 Diagnostic Loopback.......... 20 Payload Loopback.............. 20 BERT and Loopback Interaction .......... 20
7.5.1 7.5.2 7.5.3 7.5.4
7.6 7.7 7.8 7.9 7.10
COMMON AND LINE INTERFACE REGISTERS ......... 22
Master Status Register (MSR) .... 28
7.6.1
DS3/E3 FRAMER ..... 32
DS3/E3 Framer Register Description......... 32
7.7.1
DS3/E3 PERFORMANCE ERROR COUNTERS ........ 42 BERT....... 45
BERT Register Description ......... 45
7.9.1
HDLC CONTROLLER ...... 53
Receive Operation ............. 53
7.10.1
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 7.10.2 7.10.3 Transmit Operation ............ 54 HDLC Register Description ......... 54
7.11
7.11.1
FEAC CONTROLLER ...... 62
FEAC Register Description ......... 63
8.
OPERATION DETAILS ........ 67 8.1 8.2 8.3 8.4 8.5 RESET ...... 67 DS3 AND E3 MODE CONFIGURATION ......... 67 LIU AND SYSTEM INTERFACE CONFIGURATION........... 67 LOOPBACK MODES ............ 68 TRANSMIT OVERHEAD INSERTION...... 68 JTAG TAP CONTROLLER STATE MACHINE .......... 69 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS.... 71 JTAG SCAN REGISTERS.... 72
9.
JTAG INFORMATION .......... 69 9.1 9.2 9.3
10. DC ELECTRICAL CHARACTERISTICS ...... 73 11. AC TIMING CHARACTERISTICS ....... 74 11.1 11.2 11.3 SYSTEM INTERFACE TIMING ........... 74 MICROPROCESSOR INTERFACE TIMING.... 76 JTAG INTERFACE TIMING ........ 81
12. PIN ASSIGNMENTS ............ 82 13. PACKAGE INFORMATION.. 87 14. THERMAL INFORMATION .. 88 15. REVISION HISTORY............ 88
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
LIST OF FIGURES
Figure 1-1. Block Diagram ..... 6 Figure 2-1. Application Example: 12-Port Unchannelized DS3/E3 Card ........ 6 Figure 5-1. Transmit Formatter Timing ........ 11 Figure 5-2. Receive Framer Timing ............. 13 Figure 6-1. Status Register Interrupt Flow ............ 17 Figure 7-1. Transmit Data Block Diagram.... 18 Figure 7-2. Transmit Clock Block Diagram ........... 19 Figure 7-3. Receiver Block Diagram ............ 19 Figure 7-4. MSR Status Bit Interrupt Signal Flow.. 31 Figure 7-5. T3E3SR Status Bit Interrupt Signal Flow ........... 39 Figure 7-6. BERT Status Bit Interrupt Signal Flow ......... 50 Figure 7-7. HDLC Status Bit Interrupt Signal Flow......... 59 Figure 7-8. FEAC Status Bit Interrupt Signal Flow ......... 65 Figure 9-1. JTAG Block Diagram .. 69 Figure 9-2. JTAG TAP Controller State Machine .. 70 Figure 11-1. Data Path Timing Diagram ...... 75 Figure 11-2. Line Loopback Timing Diagram ........ 75 Figure 11-3. SCLK Clock Timing .. 76 Figure 11-4. Microprocessor Interface Timing Diagram (Nonmultiplexed).... 77 Figure 11-5. Microprocessor Interface Timing Diagram (Multiplexed) .... 79 Figure 11-6. JTAG Interface Timing Diagram ....... 81 Figure 12-1. DS3141 Pin Configuration ....... 83 Figure 12-2. DS3142 Pin Configuration ....... 84 Figure 12-3. DS3143 Pin Configuration ....... 85 Figure 12-4. DS3144 Pin Configuration ....... 86
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
LIST OF TABLES
Table 4-A. Applicable Telecommunications Standards .......... 8 Table 6-A. Register Map...... 15 Table 6-B. Status Register Set Example...... 17 Table 7-A. BERT/Loopback Interaction--Payload Bits ........ 20 Table 7-B. BERT/Loopback Interaction--Overhead Bits...... 21 Table 7-C. Common Line Interface Register Map.......... 22 Table 7-D. DS3/E3 Framer Register Map .... 32 Table 7-E. DS3 Alarm Criteria ...... 40 Table 7-F. E3 Alarm Criteria ......... 40 Table 7-G. BERT Register Map .... 45 Table 7-H. HDLC Register Map .... 54 Table 7-I. FEAC Register Map...... 63 Table 9-A. JTAG Instruction Codes ............. 71 Table 9-B. JTAG ID Code.... 72 Table 10-A. Recommended DC Operating Conditions......... 73 Table 10-B. DC Electrical Characteristics .... 73 Table 11-A. Data Path Timing ...... 74 Table 11-B. Line Loopback Timing ........ 74 Table 11-C. Microprocessor Interface Timing ....... 76 Table 11-D. JTAG Interface Timing ............. 81 Table 12-A. Pin Assignments (Sorted by Signal Name)....... 82 Table 14-A. Thermal Properties, Natural Convection........... 88 Table 14-B. Theta-JA (qJA) vs. Airflow.......... 88
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