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Part: DS3144DK
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Description: DS3144DK Quad DS3/E3 Framer Design Kit Daughter Card
Company: Maxim Integrated Products
Datasheet: Download DS3144DK datasheet File size : 570 kB
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DS3144DK Quad DS3/E3 Framer Design Kit Daughter Card
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3144 design kit is an easy-to-use evaluation board for the DS3144 quad DS3/E3 framer. It is intended to be used as a daughter card with the DK101 motherboard or the DK2000 motherboard. The DS3144DK comes complete with a DS3144 quad framer, DS3154 quad LIU, transformers, termination resistors, network connectors, and motherboard connectors. Interface to the DK101/DK2000 and Dallas' ChipView software give point-and-click access to configuration and status registers from a personal computer. On-board LEDs indicate loss-of-signal, out-of-frame, and interrupt status. An on-board FPGA contains mux logic to connect framer ports to one another or to the DK2000 in a variety of configurations.
FEATURES
§ § Demonstrates Key Functions of DS3144 Quad DS3/E3 Framer Includes DS3154 Quad LIU, Transformers, BNC Connectors, and Termination Passives for Communication with Test Equipment over Coax Compatible with DK101 and DK2000 Demo Kit Motherboards DK101/DK2000 Interface and ChipView Software Provide Point-and-Click Access to the DS3144 Register Set All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink Memory-Mapped FPGA Provides Flexible Clock/Data/Sync Connections Among Framer Ports and DK2000 Motherboard LEDs for Out-of-Frame, Loss-of-Signal, and Interrupt Easy-to-Read Silk Screen Labels Identify the Signals Associated with all Connectors, Jumpers, and LEDs
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DESIGN KIT CONTENTS
DS3144DK Board Download from www.maxim-ic.com/DS3144DK: DS3144DK Data Sheet ChipView Software
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ORDERING INFORMATION
PART DS3144DK DESCRIPTION DS3144 Design Kit Daughter Card
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REV: 071703
DS3144 DS3/E3 Framer Design Kit Daughter Card
COMPONENT LIST
DESIGNATION C1, C2, C15 C3C9, C11C14, C16, C20, C22, C23, C25C32 C10, C17, C18, C24 C19, C21 DS1, DS3DS10 DS2 J1 J2J5 J6J11 J12, J13 J14, J15 R1R5, R7R18, R23, R28R59 R6 R19R22, R69R72 R24 R25, R26 R27 R60 R61R68 T1 U1 U2 U3 U4 U5 U6 Y1 QTY 3 23 4 2 9 1 1 4 6 2 2 49 1 8 1 2 1 1 8 1 1 1 1 1 1 1 1 DESCRIPTION 0.1mF 10%, 16V ceramic capacitors (0805) 0.1mF 10%, 16V ceramic capacitors (0603) 1mF 10%, 16V ceramic capacitors (1206) 10mF 20%, 10V ceramic capacitors (1206) LED, red, SMD LED, green, SMD 10-pin connector, dual-row vertical 20-pin headers, dual-row vertical 5-pin BNC connectors, right-angle vertical 5-pin BNC connectors, right-angle 50-pin connectors, dual-row vertical 30W 5%, 1/16W resistors (0603) 470W 5%, 1/10W resistor (0805) 332W 1%, 1/10W resistors (0805) 10kW 5%, 1/10W resistor (0805) 330W 5% 1/10W MF resistors (0805) Not populated 10kW 5%, 1/10W resistor (0805) 100W 1/16W 5% resistors (0603) XFMR, XMIT/RCV, 1 to 2, SMT 32-pin Serial configuration EEPROM for Xilinx, 65kB 8pin DIP. Socketed (not populated) 1M PROM for FPGA 44-pin TQFP (not populated) 8-Pin mMAX VOUT = 2.5V or Adj Xilinx Spartan 2.5V FPGA, 20mm X 20mm 144-pin TQFP Quad DS3/E3 framer 144-pin BGA, 0°C to +70°C Quad DS3/E3/STS-1 LIU 144-pin BGA 3.3V, 34.368MHz crystal clock oscillator SUPPLIER Panasonic Phycomp Panasonic Panasonic Panasonic Panasonic Digi-Key Samtec Cambridge Kruvand Samtec Panasonic Panasonic Panasonic Panasonic Panasonic -- Panasonic Panasonic Pulse Engineering Atmel Xilinx Maxim Xilinx Dallas Semiconductor Dallas Semiconductor SaRonix PART ECJ-2VB1C104K 06032R104K7B20D ECJ-3YB1C105K ECJ-3YB1A106M LN1251C LN1351C S2012-05-ND HDR-TSW-110-14-T-D CP-BNCPC-004 UCBJR220 TFM-125-02-S-D-LC ERJ-3GEYJ300V ERJ-6GEYJ471V ERJ-6ENF3320V ERJ-6GEYJ103V ERA-6YEB331V -- ERJ-6ENF1002V ERJ-3GEYJ101V T3049 AT17LV65EUA and 61499-30831007000-ND XC18V01VQ44C_U MAX1792EUA25 XC2S50-5TQ144C DS3144 DS3154 NTH089AA3-34.368
BOARD FLOORPLAN
JTAG I/F FPGA TEST POINTS TICLKn ROCLKn TDATn RDATn TDENn RDENn TSOFn RSOFn TOHENn RECU TOHn TMEI LEDs: RLOSn and INT Port 4 BNCs Port 3 BNCs Port 2 BNCs DS3144 FRAMER DS3154 LIU Port 1 BNCs Quad Transformer
34.668 OSC
FPGA + Config Prom
LEDs: ROOFn, FPGAok
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DS3144 DS3/E3 Framer Design Kit Daughter Card
LINE-SIDE CONNECTIONS
The DS3144DK implements the transmit (Tx) and receive (Rx) line interface networks recommended in the DS3154 data sheet. The BNC connectors are labeled TX1 through TX4 and RX1 through RX4. Note that the purpose of the DS3144DK is to evaluate the DS3144 framer, not the DS3154 LIU. The DS3144DK is not an impedance-matched board and therefore has not been designed to have transmit waveforms with optimal template fit. To evaluate the analog performance of the DS3154, request a DS3154DK demo kit.
INTERFACE CONNECTORS
Two 50-pin connectors (J14, J15) on the bottom of the DS3144DK daughter card provide the processor interface, DS3 clock, and power supply from the DK2000 and DK101 motherboards. These connectors also provide a bidirectional clock/data/sync connection with the DK2000.
CONNECTION TO A COMPUTER
Refer to the DK101 and DK2000 data sheets for information. After power is applied, if the DS3144DK is working correctly, the FPGA status LED (green) is lit, the INT LED (red) on the DS3144DK is not lit, and the RLOS and ROOF LEDs (red) may or may not be lit.
QUICK SETUP (REGISTER VIEW)
1) 2) 3) 4) 5) Connect the DS3144DK daughter card to the DK101 motherboard or the DK2000 motherboard. Connect the motherboard to a PC and a power supply as described in the motherboard data sheet. Install and run the ChipView software, as described in the motherboard data sheet. ChipView offers a choice between Register View, Demo, and Terminal Mode. Select Register View. In the Definition File Assignment window, select the file DS3144DC_FPGA.def. This definition file will, in turn, load DS3154DC.def, DS3144_1_DC.def, DS3144_2_DC.def, DS3144_3_DC.def, and DS3144_4_DC.def. 6) Next the Register View Screen appears, showing the register names, acronyms, and values for the DS3144, DS3154, and the FPGA. Select among the register views using the pulldown menu box on the right. Several register initialization (.INI) files are available for the DS3144DK. Initialization files are loaded by selecting the menu option FileŽRegister .INI FileŽLoad .INI File. 7) Load the .INI file DS3144_1_txPRBS215-1_Cbit.ini. 8) Switch to the DS3154 register view (DS3154DC.def) and set TCR1 = 0 and RCR1 = 0 on the DS3154 (this clears the transmit tri-state and receive tri-state bits that are set on power-up in the DS3154). 9) Loopback port 1 by either (a) connecting a length of coax cable between the TX1 BNC and the RX1 BNC, or (b) setting the GCR1:LLB (local loopback) bit in the DS3154. 10) Switch to the DS3144 port 1 register view (DS3144_1_DC.def). Toggle BCR1:TC high then low to begin 15 transmitting a 2 - 1 PRBS pattern. Toggle BCR1:RESYNC high then low to resynchronize the BERT receiver. 11) At this point the following may be observed: ˇ Port 1 RLOS and ROOF LEDs are not lit, meaning the port 1 framer has acquired frame sync. This can also be observed in the port 1 T3E3SR status register. 15 ˇ The port 1 BSR:SYNC bit is set, indicating the BERT receiver is receiving the 2 - 1 PRBS pattern. This is a very basic setup designed to build familiarity with the DS3144DK. Many other configurations are possible. Consult the DS3144 data sheet and the remainder of this data sheet for further information.
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DS3144 DS3/E3 Framer Design Kit Daughter Card
MEMORY MAP
DK101 daughter card address space begins at 0x81000000. DK2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 All offsets in Table 1 below are relative to the beginning of the daughter card address space.
Table 1. Daughter Card Address Map
DS3/E3 PORT NUMBER 1 2 3 4 DS3144 OFFSET 0x1300 to 0x13FF 0x1000 to 0x10FF 0x1100 to 0x11FF 0x1200 to 0x12FF DS3154 OFFSET 0x2030 to 0x203F 0x2010 to 0x201F 0x2020 to 0x202F 0x2000 to 0x200F FPGA OFFSET 0x0010 to 0x001F 0x0020 to 0x002F 0x0030 to 0x003F 0x0040 to 0x004F
All offsets in Table 2 below are relative to the daughter card address space plus the DS3/E3 port offset in Table 1.
Table 2. DS3144DK FPGA Register Map
OFFSET 0x0000 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x000A 0x000B 0x000C 0x000D 0x000E 0x0010 0x0020 0x0030 0x0040 0x0011 0x0021 0x0031 0x0041 0x0012 0x0022 0x0032 0x0042 REGISTER BID XBIDH XBIDM XBIDL BREV AREV PREV PCTC_SR PCTS_SR PCRX_SR PCRC_SR PCRS_SR TDAT_SR TYPE Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Control Control Control Control Control Control DESCRIPTION Board ID High Nibble Extended Board ID Middle Nibble Extended Board ID Low Nibble Extended Board ID Board Fab Revision Board Assembly Revision PLD Revision PCM_TXCLK Source PCM_TSYNC Source PCM_RXD Source PCM_RXCLK Source PCM_RSYNC Source DS3144 TDAT Source
TICK_SR
Control
DS3144 TICLK Source
TSOF_SR
Control
DS3144 TSOF Source
Registers in the FPGA can be easily modified using the ChipView software and the definition file named DS3144DC_FPGA.def. Registers 0x00 through 0x07 (excluding register 0x01, which has no function on the DS3144DK) are read-only and are programmed at the factory to document board identification and revision information. The remaining registers in the FPGA control the connection of the DS3144's equipment-side framer pins. With these control registers, the framers within the DS3144 can be looped back on themselves externally, connected to each other back-to-back, or connected to the DK2000 motherboard.
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DS3144 DS3/E3 Framer Design Kit Daughter Card In Table 2 and the control register descriptions below, PCM_TXCLK, PCM_TXD, and PCM_TSYNC are clock/data/sync lines over which the DS3144 can transmit a DS3/E3 data stream to the DK2000 motherboard or other daughter cards plugged into the DK2000. PCM_RXCLK, PCM_RXD, and PCM_RSYNC are clock/data/sync lines over which the DS3144DK can receive a DS3/E3 data stream from the DK2000 or a daughter card plugged into the DK2000. See the DS3144DK schematics for additional details. Note that the DS3/E3 port numbers of the DS3144DK (as silk-screened on the board) do not match the DS3144 port numbers and the DS3154 port numbers. Table 3 details the mapping of device port numbers to board port numbers. This mapping is reflected in the address ranges shown in Table 1.
Table 3. Relationship of Silk-Screened Port Numbers to IC Ports Numbers
SILK-SCREENED PORT NUMBER ON BNCs AND RLOS/ROOF LEDs 1 2 3 4 DS3144 PORT 4 1 2 3 DS3154 PORT 4 2 3 1
From this it can be seen that, for example, the BNCs and LEDs for DS3144DK port 4 are associated with port 3 of the DS3144 and port 1 of the DS3154.
CONTROL REGISTERS
Register Name: Register Description: Register Address Offset: Bit # Name Default 7 -- -- 6 -- -- PCTC_SR PCM_TXCLK Source 0x0A 5 -- -- 4 -- -- 3 -- -- 2 PCS2 0 1 PCS1 0 0 PCS0 0
Bits 2 to 0: PCM_TXCLK Source (PCS[2:0]) 000 = Tri-state PCM_TXCLK 001 = Drive PCM_TXCLK with TDEN/TGCLK1 010 = Drive PCM_TXCLK with TDEN/TGCLK2 011 = Drive PCM_TXCLK with TDEN/TGCLK3 100 = Drive PCM_TXCLK with TDEN/TGCLK4 Register Name: Register Description: Register Address Offset: Bit # Name Default 7 -- -- 6 -- -- PCTS_SR PCM_TSYNC Source 0x0B 5 -- -- 4 -- -- 3 -- -- 2 PSS2 0 1 PSS1 0 0 PSS0 0
Bits 2 to 0: PCM_TSYNC Source (PSS[2:0]) 000 = Tri-state PCM_TSYNC 001 = Drive PCM_TSYNC with TSOF1 010 = Drive PCM_TSYNC with TSOF2 011 = Drive PCM_TSYNC with TSOF3 100 = Drive PCM_TSYNC with TSOF4 Note: Only use non-zero settings of PSS[2:0] when the TSOFx pin is configured as an output by setting MC3:TSOFC = 1 in the corresponding DS3144 framer. 5 of 9
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